Sixth international symposium on quality electronic design (isqed'05)最新文献

{"title":"Meeting nanometer DPM requirements through DFT","authors":"J. Jahangiri, D. Abercrombie","doi":"10.1109/ISQED.2005.76","DOIUrl":"https://doi.org/10.1109/ISQED.2005.76","url":null,"abstract":"As nanometer technology has increased the functionality of integrated circuits, so has it also presented challenges to acceptable yield levels. With defects per million (DPM) rates increasing, designers and manufacturers are looking for ways to enhance yield outcome. Improvements can be made by screening for defects more efficiently or by eliminating the issues leading to defects, which is the basis for any design for manufacturing (DFM) methodology. Standard test practices have become less effective for nanometer designs. However, advanced test methods show improvements can be made in three areas: increased defect coverage, increased yield learning and decreased cost.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121063438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and design of chip-package interface","authors":"A. Devgan, L. Daniel, B. Krauter, Lei He","doi":"10.1109/ISQED.2005.78","DOIUrl":"https://doi.org/10.1109/ISQED.2005.78","url":null,"abstract":"Summary form only given. Signal integrity (SI) and power integrity are forecast to be paramount issues for future chip and package designs. Larger numbers of IOs, higher frequencies, and tighter noise margins necessitate the merging of the design paradigms for chip IO and package. We shed light on a new chip-package codesign paradigm and all the technologies necessary to enable it. We first discuss parameterized reduced order models accounting for all high frequency SI effects in the package that can be reliably and automatically extracted by field solvers. We then introduce package-aware chip IO planning and placement, which is the key to chip-packaging codesign. Finally, we cover detailed power and signal integrity modeling and optimization in package.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125168828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Buffer planning algorithm based on partial clustered floorplanning","authors":"Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng","doi":"10.1109/ISQED.2005.27","DOIUrl":"https://doi.org/10.1109/ISQED.2005.27","url":null,"abstract":"In this paper, we propose a partial clustered floorplanning methodology with buffer planning. The theoretic analyses show that the timing constraints can be transferred into bounding box constraint and the spacing between buffers is somewhat stable. Therefore the critical nets can be controlled by the clustering strategy. The cluster strategies in our approach are designed not only for localizing the critical nets, but also for facilitating the buffer insertion of long wires. Based on the CBL representation, we devise sub CBL to represent the cluster and embed the optimization of the clusters into the annealing process. In most of the previous clustering-based methods, the shape of the cluster was restricted to a square. In this paper, however, we remove this restriction by treating the cluster as the sub packing. Our method can achieve a very stable performance. Experimental results on the MCNC benchmark show the effectiveness of the method and prove the correctness of the theoretic analyses.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126599024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Combining system level modeling with assertion based verification","authors":"A. Dahan, D. Geist, L. Gluhovsky, Dmitry Pidan, Gil Shapir, Y. Wolfsthal, Lyes Benalycherif, Romain Kamdem, Younes Lahbib","doi":"10.1109/ISQED.2005.32","DOIUrl":"https://doi.org/10.1109/ISQED.2005.32","url":null,"abstract":"Assertion based verification (ABV) using the PSL language is currently gaining acceptance as an essential method for functional verification of hardware. A basic technique to implement ABV is to embed temporal assertions in RTL code. The paper describes the use of a PSL-based ABV methodology in a C++-based system level modeling and simulation environment. We describe the considerations of porting a tool, which translates PSL to VHDL/Verilog, to support C++, a language which was designed for software and does not have concurrent language constructs. The translation scheme is shown to be adaptable to all C-based environments. We exemplify the wide applicability of this scheme by detailing its successful deployment in a SystemC-based industrial system-on-chip (SoC) project.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126748750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predicting and designing for the impact of process variations and mismatch on the trim range and yield of bandgap references","authors":"V. Gupta, G. Rincón-Mora","doi":"10.1109/ISQED.2005.99","DOIUrl":"https://doi.org/10.1109/ISQED.2005.99","url":null,"abstract":"Process tolerance and device mismatch produce significant random variations in bandgap voltage reference circuits. These variations lead to errors in the reference voltage and significantly impact manufacturing cost by increasing trimming requirements and decreasing yield. Current-mirror mismatch, followed by V/sub BE/ spread, package shift, and resistor mismatch are the dominant sources of random error in bandgap reference circuits. A folded-cascode topology, often used in low voltage applications, can be optimized to effectively alleviate the effects of a mismatch in the mirroring devices. By decreasing the ratio of the current in the cascode to that of the bandgap core circuit and ascertaining the best-matched devices for implementing current-mirrors and current sources, these mismatches can be significantly reduced.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"28 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116828325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling within-die spatial correlation effects for process-design co-optimization","authors":"Paul Friedberg, Yu Cao, J. Cain, Ruth Wang, J. Rabaey, C. Spanos","doi":"10.1109/ISQED.2005.82","DOIUrl":"https://doi.org/10.1109/ISQED.2005.82","url":null,"abstract":"Within-die spatial correlation of device parameter values caused by manufacturing variations has a significant impact on circuit performance. Based on experimental and simulation results, we: (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact an the variability of circuit performance.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128382342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"How circuit analysis and yield optimization can be used to detect circuit limitations before silicon results","authors":"C. Roma, P. Daglio, G. Sandre, M. Pasotti, M. Poles","doi":"10.1109/ISQED.2005.62","DOIUrl":"https://doi.org/10.1109/ISQED.2005.62","url":null,"abstract":"This paper presents a methodology for circuit analysis and yield optimization, where the most important and interesting features are the different modules with a strong focus on circuit analysis and yield improvement of the designed integrated circuits. Moreover, the possibility to analyze and size mixed-signal circuit design by a high flexibility and interactive use of the implemented methods and algorithms has been successfully used by designers for an exhaustive analysis of all devices to understand the circuit limitations before silicon results. In this case, we mainly focus on the usage of WiCkeD, deeply integrated in the Cadence Analog Design Environment. The proposed approach leverages the integration of WCDI/WiCkeD Cadence/MunEDA tools inside the Opus Design Framework: WCDI to read and collect data from Cadence Analog Design Environment and WiCkeD for circuit analysis and optimization purposes. Furthermore, the possibility both to detect all the structural constraints (i.e. saturation condition) with feasibility analysis and to separate mismatch parameters from statistical ones to show to the user which transistor parameter pairs cause largest performance drop by the mismatch effect, allows us to check, step by step, circuit consistency and the performance behaviour over a parameter during designing phases. The possibility of exporting the Analog Design Environment data towards WiCkeD for the synthesis setup and, later on, after the yield optimization step, the ability of annotating design parameters back to the Cadence Design Framework II allowed us to formalize and verify a methodology for circuit analysis and yield improvement, whose functionality has been proven on nonvolatile memories (NVM) proprietary technologies. Two main topics are addressed in this paper: first we focus on the different WiCkeD analysis and optimization modules to show the main advantages of this methodology, where circuit analysis is no longer a \"black box\". Afterwards, we use WiCkeD to optimize a bandgap voltage reference to improve the yield, addressing designers to better understand the circuit weakness.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129444501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Floorplanning with consideration of white space resource distribution for repeater planning","authors":"Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng","doi":"10.1109/ISQED.2005.58","DOIUrl":"https://doi.org/10.1109/ISQED.2005.58","url":null,"abstract":"In this paper, we proposed an effective and efficient model to evaluate the while space resource distribution in the floorplan/placement. The model discretizes the chip with a homogeneous rectangular mesh, in which the cost of each grid depends on the white space area and the routing congestion. The model has received application in our floorplanner to plan a good white space resource distribution to favor the later stage of repeater planning. On the other hand, non-zero area white-space blocks, which will join the formation of floorplan configurations, are introduced to adjust the amount and distribution of white space resources. Finally, a novel graph-based repeater assignment algorithm is devised to achieve the repeater planning. The number of nets failing to meet the repeater insertion constraint is reduced by 15.6 % on penalty of 2.2 % area usage reduction.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129838498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Closing the gap between carry select adder and ripple carry adder: a new class of low-power high-performance adders","authors":"B. Amelifard, F. Fallah, Massoud Pedram","doi":"10.1109/ISQED.2005.131","DOIUrl":"https://doi.org/10.1109/ISQED.2005.131","url":null,"abstract":"Based on the idea of sharing two adders used in the carry select adder (CSA), a new design of a low-power high-performance adder is presented. The new adder is faster than a ripple carry adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130146490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward quality EDA tools and tool flows through high-performance computing","authors":"Aaron N. Ng, I. Markov","doi":"10.1109/ISQED.2005.125","DOIUrl":"https://doi.org/10.1109/ISQED.2005.125","url":null,"abstract":"As the scale and complexity of VLSI circuits increase, electronic design automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New-generation EDA tools must work correctly on a wider range of inputs, have more internal states, take more effort to develop, and offer fertile ground for programming mistakes. Ensuring quality of a commercial tool in realistic design flows requires rigorous simulation, non-trivial computational resources, accurate reporting of results and insightful analysis. However, time-to-market pressures encourage EDA engineers and chip designers to look elsewhere. Thus, the recent availability of cheap Linux clusters and Grids shifts the bottleneck from hardware to logistical tasks, i.e., the speedy collection, reporting and analysis of empirical results. To be practically feasible, such tasks must be automated; they leverage high-performance computing to improve EDA tools. In this work we outline a possible infrastructure solution, called bX, explore relevant use models and describe our computational experience. In a specific application, we use bX to automatically build Pareto curves required for accurate performance analysis of randomized algorithms.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131050431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}