Paul Friedberg, Yu Cao, J. Cain, Ruth Wang, J. Rabaey, C. Spanos
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Modeling within-die spatial correlation effects for process-design co-optimization
Within-die spatial correlation of device parameter values caused by manufacturing variations has a significant impact on circuit performance. Based on experimental and simulation results, we: (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact an the variability of circuit performance.