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Sixth international symposium on quality electronic design (isqed'05)最新文献

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Simulating and improving microelectronic device reliability by scaling voltage and temperature 通过缩放电压和温度来模拟和提高微电子器件的可靠性
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.110
Xiaojun Li, Joerg Walter, J. Bernstein
{"title":"Simulating and improving microelectronic device reliability by scaling voltage and temperature","authors":"Xiaojun Li, Joerg Walter, J. Bernstein","doi":"10.1109/ISQED.2005.110","DOIUrl":"https://doi.org/10.1109/ISQED.2005.110","url":null,"abstract":"The purpose of this work is to explore how device operation parameters such as switching speed and power dissipation scale with voltage and temperature. We simulated a CMOS ring oscillator under different stress conditions to determine the accurate scaling relations of these operating parameters. Reduced voltage, frequency and temperature applied to a device will reduce its internal stresses, leading to an improvement of device reliability. Since all these variations for a single device are proportional, the ratios can be applied to a full circuit and help to simplify the derating model and formulate practical design guidelines for system developers to derate devices for long life applications.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134465525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of a 10 bit TSMC 0.25 /spl mu/m CMOS digital to analog converter 10位台积电0.25 /spl μ m CMOS数模转换器的设计
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.42
J. Huynh, B. Ngo, M. Pham, Lili He
{"title":"Design of a 10 bit TSMC 0.25 /spl mu/m CMOS digital to analog converter","authors":"J. Huynh, B. Ngo, M. Pham, Lili He","doi":"10.1109/ISQED.2005.42","DOIUrl":"https://doi.org/10.1109/ISQED.2005.42","url":null,"abstract":"The goal of this project is to implement a 10-bit segmented current steering TSMC 0.25 /spl mu/m CMOS digital to analog converter. Binary coded 10-bit data is input to the converter. The converter converts all combinations of ten bits from digital form into the corresponding \"staircase\" voltage levels. A low pass filter placed after the output terminal of the converter is necessary to make the voltage level smooth.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122070031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A fast lithography verification framework for litho-friendly layout design 用于光刻友好布局设计的快速光刻验证框架
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.5
Y. Ban, S. Choi, Ki-Hung Lee, Dong-Hyun Kim, Jisuk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, J. Kong
{"title":"A fast lithography verification framework for litho-friendly layout design","authors":"Y. Ban, S. Choi, Ki-Hung Lee, Dong-Hyun Kim, Jisuk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, J. Kong","doi":"10.1109/ISQED.2005.5","DOIUrl":"https://doi.org/10.1109/ISQED.2005.5","url":null,"abstract":"The increase in pattern complexity due to optical proximity correction (OPC), the tight requirements for critical dimension (CD) control and the difficulties in defect inspections make IC manufacture more expensive. To alleviate the high cost, manufacturing requirements must be handled at the design stage to improve the quality and yield of ICs. We demonstrate the extraction of critical areas for detecting failures and a new lithography simulation method for full-chip level optical proximity corrected layout. The methodology has been used in our mask verification process that is called litho-friendly layout (LFL). For the critical area extraction, we present three approaches using process window, normalized image log-slope (NILS) and edge placement error (EPE). For full-chip level simulation, we introduce an automatic calibration method for simulation process parameters, a mask decomposition method and a selective simulation method. The verification process includes lithography process simulation, print-image based LVS (layout vs. schematic) and DRC (design rule check). We also demonstrate that LFL can provide guidelines for better OPC of sub-80 nm processes.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123953667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Obstacle-avoiding rectilinear minimum-delay Steiner tree construction towards IP-block-based SOC design 面向ip块SOC设计的避障线性最小延迟Steiner树构造
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.86
Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang
{"title":"Obstacle-avoiding rectilinear minimum-delay Steiner tree construction towards IP-block-based SOC design","authors":"Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang","doi":"10.1109/ISQED.2005.86","DOIUrl":"https://doi.org/10.1109/ISQED.2005.86","url":null,"abstract":"With system-on-chip design, IP blocks form routing obstacles that deteriorate global interconnect delay. In this paper we present a new approach for obstacle-avoiding rectilinear minimal delay Steiner tree (OARMDST) construction. We formalize the solving of minimum delay tree through the concept of an extended minimization function, and trade the objective into a top-down recursion, which wisely produces delay minimization from source to critical sinks. We analyze the topology generation with treatment of obstacles and exploit the connection flexibilities. To our knowledge, this is the first in-depth study of the OARMDST problem based on topological construction. Experimental results are given to demonstrate the efficiency of the algorithm.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126154146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Interconnect delay and slew metrics using the first three moments 使用前三个力矩互连延迟和回转指标
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.67
Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye
{"title":"Interconnect delay and slew metrics using the first three moments","authors":"Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye","doi":"10.1109/ISQED.2005.67","DOIUrl":"https://doi.org/10.1109/ISQED.2005.67","url":null,"abstract":"Efficient and highly accurate interconnect delay and slew computation is critical for physical synthesis and static timing analysis. Elmore delay is a simple and closed-form metric, but it has too low an accuracy. Some higher order moments metrics such as AWE can have high accuracy, but we cannot afford their calculation speeds. In this paper we propose two closed-form delay metrics and two closed-from slew metrics using the first three moments, which can be used for both step input and ramp input.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130061472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reticle floorplanning and wafer dicing for multiple project wafers 多项目晶圆片的平面规划和晶圆切割
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.106
Meng-Chiou Wu, Rung-Bin Lin
{"title":"Reticle floorplanning and wafer dicing for multiple project wafers","authors":"Meng-Chiou Wu, Rung-Bin Lin","doi":"10.1109/ISQED.2005.106","DOIUrl":"https://doi.org/10.1109/ISQED.2005.106","url":null,"abstract":"A multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper, we propose two MILP models for the simultaneous reticle floorplanning and wafer dicing problem, a formulation for the reticle floorplanning problem which either deals with a pre-selected reticle size or incorporates reticle size optimization into a floorplanning process, and two ILP models and a simulated annealing implementation for wafer dicing. Production volume requirement and chip replication are considered in reticle floorplanning to enhance dicing yield. Although our methods take longer to produce a floorplan, the floorplan results in better dicing yield than that obtained by previous work.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126511963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A balanced scorecard for systemic quality in electronic design automation: an implementation method for an EDA company 电子设计自动化系统质量的平衡计分卡:EDA公司的实施方法
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.1
Jasjeet Kaur
{"title":"A balanced scorecard for systemic quality in electronic design automation: an implementation method for an EDA company","authors":"Jasjeet Kaur","doi":"10.1109/ISQED.2005.1","DOIUrl":"https://doi.org/10.1109/ISQED.2005.1","url":null,"abstract":"As the semiconductor industry moves into the next generation sub-nanometer design the quality of the electronic design automation (EDA) tools becomes more critical. With shrinking market windows and increasing time to market constraints the designers need reliable and robust EDA software tools to ensure that the design is manufacturable with an acceptable yield. This paper develops a balanced scorecard for implementing systemic quality in an EDA organization.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122693181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization 动态脉冲MTCMOS与总线编码的总功率和串扰最小化
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.49
H. Singh, R. Rao, D. Sylvester, Richard B. Brown, K. Nowka
{"title":"Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization","authors":"H. Singh, R. Rao, D. Sylvester, Richard B. Brown, K. Nowka","doi":"10.1109/ISQED.2005.49","DOIUrl":"https://doi.org/10.1109/ISQED.2005.49","url":null,"abstract":"Increased buffer insertion along on-chip global lines and the increasing contribution of leakage power have resulted in buffer leakage emerging as one of the chief contributors to system leakage power. We present a novel power-gating scheme for repeaters on global bus lines that address the pressing problem of runtime leakage while simultaneously eliminating worst-case capacitive coupling between adjacent bus lines. We propose using a pulsed MTCMOS (multiple threshold CMOS) scheme that dynamically activates the bus system only when transmitting a signal. Additionally, a bus encoding scheme is used to eliminate worst-case coupling and thereby negate the power-gating and pulse generation performance penalty. We consider all sources of delay and leakage power, including that of the MTCMOS control circuitry. This technique can result in nearly a 30% reduction in total bus system power for low switching activities and up to 2.3 times reduction in standby mode leakage with no reactivation delay penalty.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Evaluation of capacitor ratios in automated accurate common-centroid capacitor arrays 自动精确共质心电容器阵列中电容器比率的评估
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.54
D. Khalil, M. Dessouky, V. Bourguet, M. Louërat, A. Cathelin, H. Ragai
{"title":"Evaluation of capacitor ratios in automated accurate common-centroid capacitor arrays","authors":"D. Khalil, M. Dessouky, V. Bourguet, M. Louërat, A. Cathelin, H. Ragai","doi":"10.1109/ISQED.2005.54","DOIUrl":"https://doi.org/10.1109/ISQED.2005.54","url":null,"abstract":"In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. Precision capacitor ratios are compared using a switched-capacitor biquad and a pseudo-floating gate configuration. The test chip is used to evaluate the effectiveness of an automatic common-centroid capacitor array generation tool with arbitrary capacitor ratios. Results indicate significant improvements in ratio accuracy, which have a direct impact on a wide range of applications such as filters for wireless communications, hard drives, and high precision baseband processing.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130351441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A technique for designing totally self-checking domino logic circuits 一种设计完全自检多米诺逻辑电路的技术
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.14
C. Tang, P. Lala, J. Parkerson
{"title":"A technique for designing totally self-checking domino logic circuits","authors":"C. Tang, P. Lala, J. Parkerson","doi":"10.1109/ISQED.2005.14","DOIUrl":"https://doi.org/10.1109/ISQED.2005.14","url":null,"abstract":"A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the self-checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"105 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114019420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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