Obstacle-avoiding rectilinear minimum-delay Steiner tree construction towards IP-block-based SOC design

With system-on-chip design, IP blocks form routing obstacles that deteriorate global interconnect delay. In this paper we present a new approach for obstacle-avoiding rectilinear minimal delay Steiner tree (OARMDST) construction. We formalize the solving of minimum delay tree through the concept of an extended minimization function, and trade the objective into a top-down recursion, which wisely produces delay minimization from source to critical sinks. We analyze the topology generation with treatment of obstacles and exploit the connection flexibilities. To our knowledge, this is the first in-depth study of the OARMDST problem based on topological construction. Experimental results are given to demonstrate the efficiency of the algorithm.