Reticle floorplanning and wafer dicing for multiple project wafers

Abstract

A multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper, we propose two MILP models for the simultaneous reticle floorplanning and wafer dicing problem, a formulation for the reticle floorplanning problem which either deals with a pre-selected reticle size or incorporates reticle size optimization into a floorplanning process, and two ILP models and a simulated annealing implementation for wafer dicing. Production volume requirement and chip replication are considered in reticle floorplanning to enhance dicing yield. Although our methods take longer to produce a floorplan, the floorplan results in better dicing yield than that obtained by previous work.