A fast lithography verification framework for litho-friendly layout design

Abstract

The increase in pattern complexity due to optical proximity correction (OPC), the tight requirements for critical dimension (CD) control and the difficulties in defect inspections make IC manufacture more expensive. To alleviate the high cost, manufacturing requirements must be handled at the design stage to improve the quality and yield of ICs. We demonstrate the extraction of critical areas for detecting failures and a new lithography simulation method for full-chip level optical proximity corrected layout. The methodology has been used in our mask verification process that is called litho-friendly layout (LFL). For the critical area extraction, we present three approaches using process window, normalized image log-slope (NILS) and edge placement error (EPE). For full-chip level simulation, we introduce an automatic calibration method for simulation process parameters, a mask decomposition method and a selective simulation method. The verification process includes lithography process simulation, print-image based LVS (layout vs. schematic) and DRC (design rule check). We also demonstrate that LFL can provide guidelines for better OPC of sub-80 nm processes.