Sixth international symposium on quality electronic design (isqed'05)最新文献_第3页

Standard cell printability grading and hot spot detection 标准单元印刷性分级和热点检测

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.113

M. Côté, P. Hurat

{"title":"Standard cell printability grading and hot spot detection","authors":"M. Côté, P. Hurat","doi":"10.1109/ISQED.2005.113","DOIUrl":"https://doi.org/10.1109/ISQED.2005.113","url":null,"abstract":"Prior to 90nm the main contributor to yield loss was particle contamination. Random particle defects were directly proportional to particle density and chip size. To maximize yield, manufacturing was done in clean rooms where particles were reduced to a minimum. Yield was then directly proportional to the chip size. At 90nm and below, systematic defects play major roles in yield. Two designs of the same size can result in very different yield. This paradigm shift is caused by the printability problems that are inherent to process technologies operating in the sub-wavelength regime. The technology for printing patterns on silicon has not kept up with Moore's law. The wavelength of lithography equipment is as much as 6 times larger than the silicon features. This results in greater variation on silicon, which directly affects yield. How the design is implemented is becoming as important as how small you make it. Even at the standard cell level different solutions can demonstrate increased sensitivity to particles, short, opens, gate leakage and other yield issue. We present in this paper a methodology for grading how well standard cells will print on silicon. Using standard cell layouts, we predict a silicon image under different process conditions and take CD measurements on these images. These measurements are converted into a printability factor for each cell. This printability factor is used to grade cells and identify which cells have the largest impact on printability and which should be optimized. To help with this optimization the measurements are also used to mark printability hot spots in the cell layouts.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124707955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Reduced test application time based on reachability analysis 减少了基于可达性分析的测试应用时间

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.102

T. Haniotakis, S. Tragoudas, G. Pani

引用次数: 0

A new method for design of robust digital circuits 一种鲁棒数字电路设计的新方法

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.11

D. Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, M. Horowitz, Stephen P. Boyd

{"title":"A new method for design of robust digital circuits","authors":"D. Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, M. Horowitz, Stephen P. Boyd","doi":"10.1109/ISQED.2005.11","DOIUrl":"https://doi.org/10.1109/ISQED.2005.11","url":null,"abstract":"As technology continues to scale beyond 100 nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional circuit optimization methods assuming deterministic gate delays produce a flat \"wall\" of equally critical paths, resulting in variation-sensitive designs. This paper describes a new method for sizing of digital circuits, with uncertain gate delays, to minimize their performance variation leading to a higher parametric yield. The method is based on adding margins on each gate delay to account for variations and using a new \"soft maximum\" function to combine path delays at converging nodes. Using analytic models to predict the means and standard deviations of gate delays as polynomial functions of the device sizes, we create a simple, computationally efficient heuristic for uncertainty-aware sizing of digital circuits via geometric programming. Monte-Carlo simulations on custom 32 bit adders and ISCAS'85 benchmarks show that about 10 % to 20 % delay reduction over deterministic sizing methods can be achieved, without any additional cost in area.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122096780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 63

Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models 利用BSIM3和VBIC模型建模电路级ESD仿真的MOS snapback

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.81

Y. Zhou, D. Connerney, Ronald Carroll, T. Luk

引用次数: 30

Using MUXs network to hide bunches of scan chains 利用MUXs网络隐藏扫描链束

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.127

Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li

引用次数: 0

Wire planning with bounded over-the-block wires 使用有界的跨块线进行线路规划

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.130

Hua Xiang, I-Min Liu, Martin D. F. Wong

引用次数: 1

Performance-driven OPC for mask cost reduction 性能驱动的OPC掩膜成本降低

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.93

Puneet Gupta, A. Kahng, D. Sylvester, Jie Yang

{"title":"Performance-driven OPC for mask cost reduction","authors":"Puneet Gupta, A. Kahng, D. Sylvester, Jie Yang","doi":"10.1109/ISQED.2005.93","DOIUrl":"https://doi.org/10.1109/ISQED.2005.93","url":null,"abstract":"With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RET) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC adds complex features to the layout, resulting in mask data volume explosion and increased mask costs. Traditionally the mask flow has suffered from a lack of design information, such that all features (whether critical or non-critical) are treated alike by RET insertion. Gupta et al. (2003) proposes to exploit design information (timing slacks) to reduce OPC data volume, but has a number of impractical aspects. In this paper, we propose an implementable flow that drives model-based OPC explicitly by timing constraints, with the objective of reducing mask data volume and OPC runtime. We apply a mathematical programming based slack budgeting algorithm to determine edge placement error (EPE) tolerance budgets for all polysilicon gate geometries. These tolerances are then enforced by a commercial OPC tool to achieve up to 24% MEBES data volume and 41% OPC runtime reductions on a suite of six testcases implemented in Artisan TSMC 0.13 /spl mu/m libraries.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126298579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Noise aware decoupling capacitors for multi-voltage power distribution systems 多电压配电系统的噪声感知去耦电容器

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.84

M. Popovich, E. Friedman

{"title":"Noise aware decoupling capacitors for multi-voltage power distribution systems","authors":"M. Popovich, E. Friedman","doi":"10.1109/ISQED.2005.84","DOIUrl":"https://doi.org/10.1109/ISQED.2005.84","url":null,"abstract":"Multiple power supply voltages are often used in modern high performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described. In order to minimize the total impedance of a multi-voltage power delivery system as seen from a particular power supply, a decoupling capacitor is placed between the power supplies. The noise at one power supply can couple into the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered. The dependence of the magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. It is shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoot in the response of a dual voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121969366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Leakage current modeling in PD SOI circuits PD SOI电路的漏电流建模

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.74

M. Nanua, D. Blaauw, C. Oh

引用次数: 3

Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning 基于供应门控和高效扫描分区的每扫描一次测试BIST的功耗降低

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.96

S. Bhunia, H. Mahmoodi, D. Ghosh, K. Roy

{"title":"Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning","authors":"S. Bhunia, H. Mahmoodi, D. Ghosh, K. Roy","doi":"10.1109/ISQED.2005.96","DOIUrl":"https://doi.org/10.1109/ISQED.2005.96","url":null,"abstract":"Reduction in average and peak power during test application is important to improve battery lifetime in portable electronic devices employing periodic self-test and to improve reliability/cost of testing. This paper proposes an integrated solution for peak and average power reduction in test-per-scan BIST by targeting power reduction in both combinational block and scan chain. First, we present a novel circuit technique, called first level supply gating (FLS), to virtually eliminate power dissipation in combinational logic by masking signal transition at the logic inputs during scan shifting. We realize the masking effect by inserting an extra supply gating transistor in the VDD to GND path for the first level gates at the output of scan flip-flops. Simulation results on ISCAS89 benchmarks show an average reduction of 65% in area overhead, 119% in power overhead (in normal mode), and 104% in delay overhead compared to the lowest-cost known signal masking alternative. To reduce the leakage power of the combinational block, which is considerably high in scaled technologies, we propose input vector control using FLS during scan shifting. Experiments on a set of ISCAS89 benchmarks show about 38% average reduction in leakage power with the proposed leakage reduction technique. Second, to address the power in the scan chain, we propose an efficient scan partitioning technique that reduces both average and peak power in the scan chain during shift and functional cycles. Experiments on a set of ISCAS89 benchmarks show 12.6% average reduction in peak power with the proposed partitioning method over partitioning according to RTL description.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127966169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16