Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning

Abstract

Reduction in average and peak power during test application is important to improve battery lifetime in portable electronic devices employing periodic self-test and to improve reliability/cost of testing. This paper proposes an integrated solution for peak and average power reduction in test-per-scan BIST by targeting power reduction in both combinational block and scan chain. First, we present a novel circuit technique, called first level supply gating (FLS), to virtually eliminate power dissipation in combinational logic by masking signal transition at the logic inputs during scan shifting. We realize the masking effect by inserting an extra supply gating transistor in the VDD to GND path for the first level gates at the output of scan flip-flops. Simulation results on ISCAS89 benchmarks show an average reduction of 65% in area overhead, 119% in power overhead (in normal mode), and 104% in delay overhead compared to the lowest-cost known signal masking alternative. To reduce the leakage power of the combinational block, which is considerably high in scaled technologies, we propose input vector control using FLS during scan shifting. Experiments on a set of ISCAS89 benchmarks show about 38% average reduction in leakage power with the proposed leakage reduction technique. Second, to address the power in the scan chain, we propose an efficient scan partitioning technique that reduces both average and peak power in the scan chain during shift and functional cycles. Experiments on a set of ISCAS89 benchmarks show 12.6% average reduction in peak power with the proposed partitioning method over partitioning according to RTL description.