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Exact algorithms for coupling capacitance minimization by adding one metal layer 通过添加一个金属层来最小化耦合电容的精确算法
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.55
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
{"title":"Exact algorithms for coupling capacitance minimization by adding one metal layer","authors":"Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong","doi":"10.1109/ISQED.2005.55","DOIUrl":"https://doi.org/10.1109/ISQED.2005.55","url":null,"abstract":"Due to the rapid development of manufacturing process technology and tight marketing schedules, chip design and manufacturing always work towards an integrated solution to achieve an enhanced product for fast time-to-market and higher niche profit. For high-end \"high-volume\" products, one good option for further improving chip performance is to add extra metal layers based on an existing design after all easy circuit fixes and process tricks have been applied. This strategy has been applied by the main integrated device manufacturers. In contrast to most low volume ASIC, the additional metal layer cost is low due to cost averaging over huge volumes. We address the NLM (new layer migration) problem which eliminates coupling capacitance violations for speed push in a given routing solution by migrating some wire segments to a metal layer newly inserted under the commonly used metal filling post process for manufacturability and coupling control. We first propose an exact linear-time algorithm to judge whether a feasible solution exists or not. Then we present a provably optimal algorithm to eliminate as many coupling violations as possible. At the same time, the total coupling capacitance on both metal layers is minimized. For n wire segments, the time complexity of the algorithm is O(n/sup 3/2/log(n)). Finally, an LP approach is presented as post processing to adjust segment positions when the two layers have layer-dependent design spacing rules.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design considerations for low-power ultra wideband receivers 低功耗超宽带接收机的设计考虑
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.40
P. Heydari
{"title":"Design considerations for low-power ultra wideband receivers","authors":"P. Heydari","doi":"10.1109/ISQED.2005.40","DOIUrl":"https://doi.org/10.1109/ISQED.2005.40","url":null,"abstract":"This paper studies design considerations for low-power ultra wideband (UWB) receiver architectures. First, three different architectures for the impulse-radio UWB transceiver are studied, while investigating the power-performance trade-offs. As is elaborated in the paper, a more power-efficient architecture should undertake part of the signal processing in the analog-domain. Next, the multiband UWB transceiver is studied and power-efficient circuits for the front-end of the UWB transceiver are presented. Finally, the performance and power consumption of these transceivers are compared and a number of design indications are provided.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115579783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Analysis for complex power distribution networks considering densely populated vias 考虑密集过孔的复杂配电网分析
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.19
Young-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, J. Kong
{"title":"Analysis for complex power distribution networks considering densely populated vias","authors":"Young-Seok Hong, Heeseok Lee, Joon-Ho Choi, Moon-Hyun Yoo, J. Kong","doi":"10.1109/ISQED.2005.19","DOIUrl":"https://doi.org/10.1109/ISQED.2005.19","url":null,"abstract":"Due to the high speed and low power trends, the power distribution network (PDN) in multilayer printed circuit boards (PCBs) plays a pivotal role in terms of system performance. The paper presents an efficient analysis method for the irregularly shaped power/ground plane pair considering the effect of densely populated power/ground and signal vias in the frequency domain. The plane is divided based on geometric properties and modeled by the parallel-plate transmission line theory. For examination of various via effects, we have modeled vias according to their properties, such as power, ground and signal. Using a conventional circuit simulator, the input- and trans-impedance of power/ground planes are investigated. Since the proposed method is accurate as well as fast, it can be efficiently applied to multilayered PCB structures at the early design stage.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115482183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reliability-centric hardware/software co-design 以可靠性为中心的硬件/软件协同设计
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.104
S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie, W. Hung
{"title":"Reliability-centric hardware/software co-design","authors":"S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie, W. Hung","doi":"10.1109/ISQED.2005.104","DOIUrl":"https://doi.org/10.1109/ISQED.2005.104","url":null,"abstract":"This paper proposes a reliability-centric hardware/software co-design framework. This framework operates with a component library that provides multiple alternates for a given task, each of which is potentially different from the others in terms of reliability, performance, and area metrics. The paper also presents an experimental evaluation of the proposed co-design framework using several example designs and a comparison to a conventional co-design method that does not consider reliability. Our experimental evaluation demonstrates that the proposed framework can be used to study the tradeoffs between area, performance, and reliability and that it is important to include reliability as a first class parameter in optimization.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126824249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Power supply noise-aware scheduling and allocation for DSP synthesis 基于DSP合成的电源噪声感知调度与分配
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.97
Dongku Kang, Yiran Chen, K. Roy
{"title":"Power supply noise-aware scheduling and allocation for DSP synthesis","authors":"Dongku Kang, Yiran Chen, K. Roy","doi":"10.1109/ISQED.2005.97","DOIUrl":"https://doi.org/10.1109/ISQED.2005.97","url":null,"abstract":"As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for high-level synthesis. By evaluating power supply noise in the early design stage, the proposed method generates schedule and resource allocation with a floorplan such that the power supply noise is minimized. To achieve the goal, we formulated the problem using a genetic algorithm. Compared to designs that do not consider supply noise, the proposed methodology reduces power supply noise up to 44%.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130114174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An interconnect insensitive linear time-varying driver model for static timing analysis 一种用于静态时序分析的互连不敏感线性时变驱动模型
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.16
Chung-Kuan Tsai, M. Marek-Sadowska
{"title":"An interconnect insensitive linear time-varying driver model for static timing analysis","authors":"Chung-Kuan Tsai, M. Marek-Sadowska","doi":"10.1109/ISQED.2005.16","DOIUrl":"https://doi.org/10.1109/ISQED.2005.16","url":null,"abstract":"This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the LTV model and how to apply that model in static timing analysis. With the LTV model, the delay error caused by the driver's nonlinearity is reduced significantly because the driver's linear - and saturation-region operations are characterized individually. Because both the linear- and saturation-region models are insensitive to interconnect loads, it is sufficient to use a small number of LTV models for a wide range of possible interconnect loads. Due to the same reason, the LTV model is robust, does not require iterations, and makes timing analysis fast. This method is fast and accurate compared to existing effective capacitance-based methods. Results compared with SPICE simulation demonstrate average 2.5% delay error and 4.4% slew error.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128769277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
In-circuit self-tuning of clock latencies 电路中时钟延迟的自调谐
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.65
K. Rahimi, C. Diorio
{"title":"In-circuit self-tuning of clock latencies","authors":"K. Rahimi, C. Diorio","doi":"10.1109/ISQED.2005.65","DOIUrl":"https://doi.org/10.1109/ISQED.2005.65","url":null,"abstract":"Random manufacturing variations and changes in operating conditions can alter the relative timing of data and clock signals and cause timing violations. Increasing relative magnitude of manufacturing variations and accommodating a wide range of operating conditions necessitate large design margins and decrease circuit performance. In-circuit tuning of clock latencies allows recovering some of the performance loss. In this paper, we introduce self-tuning adaptive-delay sequential elements (SASE) that use PMOS floating gates to tune clock latencies of individual flip-flops. SASE are capable of concurrent, in-circuit optimization of clock latencies under varying operating conditions. We use an explicit-pulsed flip-flop to present the SASE operations and tuning. Our experiments with fabricated prototypes show that SASE can tune their clock latencies with picosecond resolution over one half of the clock period. Our experiments also show that SASE sensitivities are comparable to non-adaptive flip-flops and do not pose any practical limitations. We also present a tuning procedure for pipeline circuits that tunes SASE clock latencies to maximize performance.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114556856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TED thermo electrical designer: a new physical design verification tool TED热电设计器:一个新的物理设计验证工具
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.119
E. Sokolowska, M. Barszcz, B. Kaminska
{"title":"TED thermo electrical designer: a new physical design verification tool","authors":"E. Sokolowska, M. Barszcz, B. Kaminska","doi":"10.1109/ISQED.2005.119","DOIUrl":"https://doi.org/10.1109/ISQED.2005.119","url":null,"abstract":"Although several types of design verification tools have recently been added to the IC design flow, adequate tools for thermal analysis during the design process do not exist. In the absence of thermal analysis, not only can excessive hot spots affect reliability, but important differences between expected and actual performances may compromise circuit functionality. We have introduced a new physical design verification tool, TED, integrating thermal analysis into the design flow. Starting from the extracted view, this tool automatically verifies for each device its temperature and power density, and checks whether maximum ratings are not exceeded. It yields a circuit simulation accounting for realistic temperature distributions without modifying device models.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122914931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
IP quality: a design, not a verification problem IP质量:一个设计问题，而不是一个验证问题
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.69
M. Keating
{"title":"IP quality: a design, not a verification problem","authors":"M. Keating","doi":"10.1109/ISQED.2005.69","DOIUrl":"https://doi.org/10.1109/ISQED.2005.69","url":null,"abstract":"Last year at ISQED, the author presented a paper describing the challenge IP providers face: customers demand zero-defect IP, yet this is beyond state of the art. This paper presents a possible path to address some of the key limiting issues described last year. Starting with an argument that verification cannot address the IP quality challenge, the paper argues that design methodology changes are the most likely path to increasing IP quality. It describes methods for measuring and reducing the state space of designs, and for representing the state space in a way that leads to more effective reasoning about the design. Finally, it discusses some recent experiments with formal and informal specification.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132238470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high-performance SRAM technology with reduced chip-level routing congestion for SoC 一种高性能SRAM技术，减少了SoC的芯片级路由拥塞
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.6
R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, A. Teene, S. Ramesh
{"title":"A high-performance SRAM technology with reduced chip-level routing congestion for SoC","authors":"R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, A. Teene, S. Ramesh","doi":"10.1109/ISQED.2005.6","DOIUrl":"https://doi.org/10.1109/ISQED.2005.6","url":null,"abstract":"High-density and high-performance single-port and dual-port SRAM increasingly occupy the majority of the chip area in deep submicron (DSM) system-on-chip (SoC) designs. A complex SoC design may include 10 Mb or more of embedded SRAM and use up to a few hundred individual memory instances with various sizes and configurations. We have previously reported on the need for high-density and high-performance SRAM with good yieldability and manufacturability and our results on 6T-SRAM bitcells in 180 nm and 130 nm generation standard CMOS processes (see Kong, W. et al., 2001; Duan, F. et al., 2003). We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance. We extend the discussion on embedded SRAM bitcell robustness and ease of manufacture to include memory and chip-level considerations, such as memory performance and routing congestion. We present our results on the advantages of using metal 2 bitline bitcells in terms of memory performance, and we highlight the advantages of providing unrestricted, or only partially restricted, routing over memory capability to chip-level routing metallization for minimizing chip-level routing congestion and, hence, improve overall chip area utilization, i.e. chip-level effective density.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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