A high-performance SRAM technology with reduced chip-level routing congestion for SoC

Abstract

High-density and high-performance single-port and dual-port SRAM increasingly occupy the majority of the chip area in deep submicron (DSM) system-on-chip (SoC) designs. A complex SoC design may include 10 Mb or more of embedded SRAM and use up to a few hundred individual memory instances with various sizes and configurations. We have previously reported on the need for high-density and high-performance SRAM with good yieldability and manufacturability and our results on 6T-SRAM bitcells in 180 nm and 130 nm generation standard CMOS processes (see Kong, W. et al., 2001; Duan, F. et al., 2003). We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance. We extend the discussion on embedded SRAM bitcell robustness and ease of manufacture to include memory and chip-level considerations, such as memory performance and routing congestion. We present our results on the advantages of using metal 2 bitline bitcells in terms of memory performance, and we highlight the advantages of providing unrestricted, or only partially restricted, routing over memory capability to chip-level routing metallization for minimizing chip-level routing congestion and, hence, improve overall chip area utilization, i.e. chip-level effective density.