An interconnect insensitive linear time-varying driver model for static timing analysis

Abstract

This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the LTV model and how to apply that model in static timing analysis. With the LTV model, the delay error caused by the driver's nonlinearity is reduced significantly because the driver's linear - and saturation-region operations are characterized individually. Because both the linear- and saturation-region models are insensitive to interconnect loads, it is sufficient to use a small number of LTV models for a wide range of possible interconnect loads. Due to the same reason, the LTV model is robust, does not require iterations, and makes timing analysis fast. This method is fast and accurate compared to existing effective capacitance-based methods. Results compared with SPICE simulation demonstrate average 2.5% delay error and 4.4% slew error.