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Analysis of wave-pipelined domino logic circuit and clocking styles subject to parametric variations 波形流水线多米诺逻辑电路及随参数变化的时钟样式分析
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.21
Wei Ling, Y. Savaria
{"title":"Analysis of wave-pipelined domino logic circuit and clocking styles subject to parametric variations","authors":"Wei Ling, Y. Savaria","doi":"10.1109/ISQED.2005.21","DOIUrl":"https://doi.org/10.1109/ISQED.2005.21","url":null,"abstract":"In recent years, wave-pipelined domino logic has received much attention as a means to implement high-speed circuits. However, this logic is vulnerable to parametric variations and the situation will degrade as technology scales down. In this paper, statistical timing relations are developed for characterizing performance impacts of parametric variations in different wave-pipelined domino circuits and clocking styles. Analytic results show that a wave pipeline built with a footless nonblocking domino cell accumulates timing variations due to parametric variation along the pipeline. Thus performance reduces with pipeline size as variations accumulate. On the other hand, wave pipelined footed blocking domino logic is less sensitive to parametric variations. Simulation results of a 6-stage wave pipeline using footed blocking domino cells in 130 nm technology also demonstrate the advantages of this logic style both in performance and power consumption.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131929744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A mask reuse methodology for reducing system-on-a-chip cost 一种降低片上系统成本的掩码复用方法
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.7
S. Bhattacharya, J. Darringer, D. Ostapko, Youngsoo Shin
{"title":"A mask reuse methodology for reducing system-on-a-chip cost","authors":"S. Bhattacharya, J. Darringer, D. Ostapko, Youngsoo Shin","doi":"10.1109/ISQED.2005.7","DOIUrl":"https://doi.org/10.1109/ISQED.2005.7","url":null,"abstract":"Today's system-on-a-chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual property (IP) or \"cores\". However, once assembled, the physical design and manufacturing process that follows does not benefit from the reuse of these cores. We propose an alternative mask reuse methodology (MRM) where most cores are provided with hardened layouts, significantly reducing the number of components for chip-level processing and the associated turn-around time. In addition, each core has a pre-verified mask set, which can be re-used to significantly reduce the overall mask cost and mask manufacturing time. Since mask cost and design and verification times are rapidly becoming prohibitive for low or even medium volume ASIC parts, the proposed MRM methodology can help reduce the barrier for ASIC parts. We provide details of the methodology, as well as an assessment of its impact on design time and design cost with an example of a network processor SoC.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133820171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design for degradation: CAD tools for managing transistor degradation mechanisms 退化设计:用于管理晶体管退化机制的CAD工具
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.41
Ananth Somayaji Goda, G. Kapila
{"title":"Design for degradation: CAD tools for managing transistor degradation mechanisms","authors":"Ananth Somayaji Goda, G. Kapila","doi":"10.1109/ISQED.2005.41","DOIUrl":"https://doi.org/10.1109/ISQED.2005.41","url":null,"abstract":"We present a set of computer-aided-design (CAD) tools to aid design of circuits in the presence of transistor degradation mechanisms. These CAD tools not only provide information on the circuit behavior due to degradation but also provide information on the degradation suffered by the individual components in the design and also provide design guidelines in the form of changes to the component parameters to bring down the degradation to specified values. These tools facilitate the designer during circuit design in the presence of degradation mechanisms like hot carrier injection (HCI) and negative bias temperature instability (NBTI).","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127927147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Concurrent chip package design for global clock distribution network using standing wave approach 基于驻波法的全球时钟配电网并行芯片封装设计
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.33
M. Shen, Lirong Zheng, E. Tjukanoff, J. Isoaho, H. Tenhunen
{"title":"Concurrent chip package design for global clock distribution network using standing wave approach","authors":"M. Shen, Lirong Zheng, E. Tjukanoff, J. Isoaho, H. Tenhunen","doi":"10.1109/ISQED.2005.33","DOIUrl":"https://doi.org/10.1109/ISQED.2005.33","url":null,"abstract":"As a result of the continuous downscaling of CMOS technology, on chip frequency for high performance microprocessors will soon reach 10 GHz, according to the international technology roadmap for semiconductors (ITRS). A 10 GHz global clock distribution network using a standing wave approach is analyzed on the chip and package levels. On the chip level, a 10 GHz standing wave oscillator (SWO) for a global clock distribution network, using 0.18 /spl mu/m IP6M CMOS technology, is designed and analyzed. Simulation results show that skew is well controlled (about 1 ps), while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On the package level, we assume that the chip size is 20/spl times/20 mm/sup 2/ and flip-chip bonding technology is used. Simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of /spl tau//sub clk/ when the attenuation is about 1.5 dB. For attenuation from 1.5 dB to 6.7 dB, the peak positions (n/spl lambda//2) can be used as clock nodes. For the mesh and plane shape, the skew is controlled within 10% of /spl tau//sub clk/ using the standing wave method.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129298465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Error analysis for the support of robust voltage scaling 支持鲁棒电压标度的误差分析
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.53
D. Roberts, T. Austin, D. Blaauw, T. Mudge, K. Flautner
{"title":"Error analysis for the support of robust voltage scaling","authors":"D. Roberts, T. Austin, D. Blaauw, T. Mudge, K. Flautner","doi":"10.1109/ISQED.2005.53","DOIUrl":"https://doi.org/10.1109/ISQED.2005.53","url":null,"abstract":"Recently, a new dynamic voltage scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the minimum supply voltage, even if occasional errors result. To determine which technique can reliably and efficiently detect such failures, it is necessary to understand the manner in which digital designs fail at critical voltages. We report hardware measurements of the failure modes of a multiplier circuit under voltage scaling. We show that even at small error rates, it is necessary to deal with multiple errors where bits are flipped from both 0 to 1 and 1 to 0. Intra- and inter-die variations make the exact nature of these flips unpredictable. This suggests that conventional single and unidirectional error detectors will not work. We conclude that the most suitable solution is a simple delay-error tolerant flip-flop that detects and corrects errors by double sampling signals.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129116011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Functions for quality transition fault tests 用于质量转换故障测试的功能
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.60
M. Michael, Stelios N. Neophytou, S. Tragoudas
{"title":"Functions for quality transition fault tests","authors":"M. Michael, Stelios N. Neophytou, S. Tragoudas","doi":"10.1109/ISQED.2005.60","DOIUrl":"https://doi.org/10.1109/ISQED.2005.60","url":null,"abstract":"The paper shows how to generate a function that contains all possible tests to detect a transition fault. Moreover, a systematic methodology is presented that derives the functions for all transition faults based on only two circuit traversals. Quality tests are generated by requiring that the function formulation considers established sensitization criteria to either activate a transition at the fault site or propagate it to a circuit output. Experimental results on the ISCAS'85 and ISCAS'89 benchmarks demonstrate the promise of the method which can also lead to efficient compaction methods for transition faults.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114361770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analytical study of impact ionization and subthreshold current in submicron n-MOSFET 亚微米n-MOSFET中冲击电离和亚阈值电流的分析研究
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.22
B. Jharia, S. Sarkar, R. P. Agarwal
{"title":"Analytical study of impact ionization and subthreshold current in submicron n-MOSFET","authors":"B. Jharia, S. Sarkar, R. P. Agarwal","doi":"10.1109/ISQED.2005.22","DOIUrl":"https://doi.org/10.1109/ISQED.2005.22","url":null,"abstract":"The effect of impact ionization in subthreshold operation of an n-MOSFET is studied. Analysis shows that the effect of impact ionization cannot be neglected in the subthreshold region of operation of the submicron MOSFET. This effect is enhanced at larger drain voltages. Gate bias and oxide thickness controls the effect of impact ionization. The effect of impact ionization is through the gate and drain bias dependence of the maximum electric field. The subthreshold current increases when the gate oxide is thinned. This is because of the increase in impact ionization due to the increase in electric field.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127411274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A minimum cut based re-synthesis approach 基于最小切割的再合成方法
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.9
M. Welling, S. Tragoudas, Haibo Wang
{"title":"A minimum cut based re-synthesis approach","authors":"M. Welling, S. Tragoudas, Haibo Wang","doi":"10.1109/ISQED.2005.9","DOIUrl":"https://doi.org/10.1109/ISQED.2005.9","url":null,"abstract":"A new re-synthesis approach that benefits from min-cut based partitioning is proposed. This divide and conquer approach is shown to improve the performance of existing synthesis tools on a variety of benchmarks.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125673656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of interconnect process variations on memory performance and design 互连过程变化对存储器性能和设计的影响
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.63
A. Teene, Bob Davis, R. Castagnetti, Jeff Brown, S. Ramesh
{"title":"Impact of interconnect process variations on memory performance and design","authors":"A. Teene, Bob Davis, R. Castagnetti, Jeff Brown, S. Ramesh","doi":"10.1109/ISQED.2005.63","DOIUrl":"https://doi.org/10.1109/ISQED.2005.63","url":null,"abstract":"Interconnect-related effects have become significant factors that can affect complex nanometer designs, such as memories. Thus, a robust memory design methodology needs to include the accurate modeling of interconnect parasitics and interconnect process variations. In this paper we present a statistical design approach to study the impact of interconnect process variations on memory performance and design. This approach uses 3D parasitic extraction, circuit simulation, Monte Carlo and sensitivity analysis to determine the parasitic and performance sensitivities to interconnect process parameter variations for a 90 nm memory design example. The sensitivity analysis results can be used to optimize the memory circuit design and layout to further improve memory performance and robustness.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124249750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Clock trees: differential or single ended? 时钟树:差分还是单端?
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.31
D. Sekar
{"title":"Clock trees: differential or single ended?","authors":"D. Sekar","doi":"10.1109/ISQED.2005.31","DOIUrl":"https://doi.org/10.1109/ISQED.2005.31","url":null,"abstract":"A low-swing differential clock distribution scheme is presented, and is compared with widely used single ended clock distribution. Test chips based on these two clocking styles are designed with 1 GHz clocks in a 90 nm technology. Low-swing differential clock trees are seen to have 25-42% less sensitivity to power supply noise and 6% less sensitivity to manufacturing variations than single ended clock trees, which leads to significant savings in skew and jitter. Another important contribution is the development of techniques to design robust single ended and differential clock trees.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122570225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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