Analysis of wave-pipelined domino logic circuit and clocking styles subject to parametric variations

Abstract

In recent years, wave-pipelined domino logic has received much attention as a means to implement high-speed circuits. However, this logic is vulnerable to parametric variations and the situation will degrade as technology scales down. In this paper, statistical timing relations are developed for characterizing performance impacts of parametric variations in different wave-pipelined domino circuits and clocking styles. Analytic results show that a wave pipeline built with a footless nonblocking domino cell accumulates timing variations due to parametric variation along the pipeline. Thus performance reduces with pipeline size as variations accumulate. On the other hand, wave pipelined footed blocking domino logic is less sensitive to parametric variations. Simulation results of a 6-stage wave pipeline using footed blocking domino cells in 130 nm technology also demonstrate the advantages of this logic style both in performance and power consumption.