Concurrent chip package design for global clock distribution network using standing wave approach

As a result of the continuous downscaling of CMOS technology, on chip frequency for high performance microprocessors will soon reach 10 GHz, according to the international technology roadmap for semiconductors (ITRS). A 10 GHz global clock distribution network using a standing wave approach is analyzed on the chip and package levels. On the chip level, a 10 GHz standing wave oscillator (SWO) for a global clock distribution network, using 0.18 /spl mu/m IP6M CMOS technology, is designed and analyzed. Simulation results show that skew is well controlled (about 1 ps), while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On the package level, we assume that the chip size is 20/spl times/20 mm/sup 2/ and flip-chip bonding technology is used. Simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of /spl tau//sub clk/ when the attenuation is about 1.5 dB. For attenuation from 1.5 dB to 6.7 dB, the peak positions (n/spl lambda//2) can be used as clock nodes. For the mesh and plane shape, the skew is controlled within 10% of /spl tau//sub clk/ using the standing wave method.