发布求助
文献互助 智能选刊 最新文献

Sixth international symposium on quality electronic design (isqed'05)最新文献

筛选
英文 中文
Power grid planning for microprocessors and SoCs 微处理器和soc的电网规划
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.95
Qing K. Zhu, D. Ayers
{"title":"Power grid planning for microprocessors and SoCs","authors":"Qing K. Zhu, D. Ayers","doi":"10.1109/ISQED.2005.95","DOIUrl":"https://doi.org/10.1109/ISQED.2005.95","url":null,"abstract":"This paper describes power grid planning methodology for high-performance microprocessors and SoC chips. It shows how to estimate currents from an existing chip to a new chip. The power grid planning and pre-layout simulation becomes important for time to market of chip design. We discuss the current scaling technique and one SoC design example. More details on the methodology can be found in Zhu (2004).","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121728818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast decap allocation algorithm for robust on-chip power delivery 快速decap分配算法的鲁棒片上功率传输
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.57
Z. Qi, Hang Li, S. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
{"title":"Fast decap allocation algorithm for robust on-chip power delivery","authors":"Z. Qi, Hang Li, S. Tan, Lifeng Wu, Yici Cai, Xianlong Hong","doi":"10.1109/ISQED.2005.57","DOIUrl":"https://doi.org/10.1109/ISQED.2005.57","url":null,"abstract":"Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. We present a fast decap allocation algorithm, which is able to confine voltage fluctuations below a user specified threshold by adding decaps in an area efficient way. The new algorithm adopts the recently proposed time-domain adjoint network method for sensitivity calculation. To avoid the time consuming line search at each iteration in the conjugate gradient method, we propose a simple, yet efficient, search step computation method to accelerate the optimization process. The experimental results show that the proposed algorithm is at least 10 times faster than the fastest conjugate gradient method reported so far with similar optimization results.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134193316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Technology mapping for reliability enhancement in logic synthesis 提高逻辑综合可靠性的技术映射
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.118
Zhaojun Wo, I. Koren
{"title":"Technology mapping for reliability enhancement in logic synthesis","authors":"Zhaojun Wo, I. Koren","doi":"10.1109/ISQED.2005.118","DOIUrl":"https://doi.org/10.1109/ISQED.2005.118","url":null,"abstract":"Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliability is commonly ignored during the logic synthesis step. A major reason for this is the fact that constructing a cost function to measure sensitivity to faults at the logic synthesis level is complex. The work presented in this paper addresses one important aspect of synthesis for high reliability. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with fault sensitivity as an optimization metric. We believe that the difficulty in obtaining accurate metrics of fault sensitivity at the technology independent level makes it hard to optimize at this level, thus technology dependent mapping offers a direct method to improve reliability. In this paper, we present a concept named \"effective fault area\" for mapping onto library gates. Along with this concept, we adopt a Markov-model based analytical method to accurately estimate fault sensitivity during mapping with a low computational overhead. Several benchmark results show that the average reliability improvement is about 20.7% at the cost of 12.1% increase in delay.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130108430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations 鲁棒多级电流模式片上互连信号在存在的过程变化
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.107
V. Venkatraman, W. Burleson
{"title":"Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations","authors":"V. Venkatraman, W. Burleson","doi":"10.1109/ISQED.2005.107","DOIUrl":"https://doi.org/10.1109/ISQED.2005.107","url":null,"abstract":"The paper presents a novel process-tolerant multi-level signaling system for on-chip interconnects. Novel multi-level driver and receiver designs are presented which are robust in the presence of process-induced parameter variation and uncertainties. Monte Carlo analyses show that the interconnect delay and total average power are normally distributed with a standard deviation of around 9.46% and 15.96% respectively for a 10 mm line in 100 nm technology. Individual parameter sensitivity analyses show that the total average power is most influenced by supply voltage and effective gate length, and delay is most influenced by interconnect resistance and capacitance. Yield of high performance and low power bins in 100 nm technology under process variations using the proposed multi-level signaling system is 36.1%, yield of high performance bins is 27.3% and yield of low power bins is 25.1% and yield of bad bins is only 11.5%.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"217 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Thermal-aware floorplanning using genetic algorithms 使用遗传算法的热感知地板规划
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.122
W. Hung, Yuan Xie, N. Vijaykrishnan, Charles Addo-Quaye, T. Theocharides, M. J. Irwin
{"title":"Thermal-aware floorplanning using genetic algorithms","authors":"W. Hung, Yuan Xie, N. Vijaykrishnan, Charles Addo-Quaye, T. Theocharides, M. J. Irwin","doi":"10.1109/ISQED.2005.122","DOIUrl":"https://doi.org/10.1109/ISQED.2005.122","url":null,"abstract":"In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while optimizing the traditional design metric, chip area. The floorplanning problem is formulated as a genetic algorithm problem, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension, and the location of modules. Area and/or temperature optimizations guide the genetic algorithm to generate the final fittest solution. The experimental results using MCNC benchmarks and a face detection chip show that our combined area and thermal optimization technique decreases the peak temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116380139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 121
Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits 超薄氧化亚50nm双栅器件和电路的栅极泄漏建模与分析
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.77
S. Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, S. Lo, R. Joshi, C. Chuang, K. Roy
{"title":"Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits","authors":"S. Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, S. Lo, R. Joshi, C. Chuang, K. Roy","doi":"10.1109/ISQED.2005.77","DOIUrl":"https://doi.org/10.1109/ISQED.2005.77","url":null,"abstract":"Double gate (DG) FET have emerged as the most promising technology for sub-50 nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, namely, doped body symmetric device (SymDG) with polysilicon gates, intrinsic body symmetric device with metal gates (MGDG) and intrinsic body asymmetric device (AsymDG) with different front and back gate materials. It is observed that, use of (near-mid-gap) metal gate and intrinsic body can result in 3-4/spl times/ reduction in gate-to-channel leakage compared to the SymDG structure.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116492463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
BIST-guided ATPG BIST-guided生成时间
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.26
Ahmad A. Al-Yamani, E. McCluskey
{"title":"BIST-guided ATPG","authors":"Ahmad A. Al-Yamani, E. McCluskey","doi":"10.1109/ISQED.2005.26","DOIUrl":"https://doi.org/10.1109/ISQED.2005.26","url":null,"abstract":"This paper presents a new reseeding technique that considerably reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without explicitly loading a seed. The ATPG process is tuned to target only undetected faults as the PRPG goes through its natural sequence which is maximally used to generate useful test patterns. The test application procedure is slightly modified to enable higher flexibility and more reduction in tester storage and test time. The results of applying the technique show up to 90% reduction in tester storage and 80% reduction in test time compared to classic reseeding. They also show 70% improvement in defect coverage when the technique is emulated on test chips.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114490759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits 片上电感对纳米级集成电路配电网设计的影响
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.64
N. Srivastava, X. Qi, K. Banerjee
{"title":"Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits","authors":"N. Srivastava, X. Qi, K. Banerjee","doi":"10.1109/ISQED.2005.64","DOIUrl":"https://doi.org/10.1109/ISQED.2005.64","url":null,"abstract":"This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chip's power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116614363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Exploring the challenges in creating a high-quality mainstream design solution for system-in-package (SiP) design 探索为系统级封装(SiP)设计创建高质量主流设计解决方案所面临的挑战
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.56
B. McCaffrey
{"title":"Exploring the challenges in creating a high-quality mainstream design solution for system-in-package (SiP) design","authors":"B. McCaffrey","doi":"10.1109/ISQED.2005.56","DOIUrl":"https://doi.org/10.1109/ISQED.2005.56","url":null,"abstract":"System-in-package (SiP) design provides a unique system integration and manufacturing capability that has clear system development benefits that span cost, time-to-market, reduced form factor and opportunity for reduction in power. Many design systems software customers are producing some form of SiP design today. However, SiP design is still considered to be an expert design process that is not scaleable as a general design solution. There are many design challenges that must be addressed before a high-quality SiP design solution can be developed that would enable SiP as a mainstream design solution. The paper demonstrates both design challenges and solution concepts for creating a high-quality design solution from system capture through manufacturing. It would be impossible to address the details of the entire SiP design challenges properly in a single paper; therefore this paper focuses on \"some\" of the key design challenges that have a significant impact on design tools, methods and flows. The design solution gap between current capabilities and practices, and what is required for SiP are used to guide the arguments presented.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127375533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Two-dimensional layout migration by soft constraint satisfaction 基于软约束的二维布局迁移
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.126
Qianying Tang, Jianwen Zhu
{"title":"Two-dimensional layout migration by soft constraint satisfaction","authors":"Qianying Tang, Jianwen Zhu","doi":"10.1109/ISQED.2005.126","DOIUrl":"https://doi.org/10.1109/ISQED.2005.126","url":null,"abstract":"Layout migration has re-emerged as an important task due to the increasing use of library hard intellectual properties. While recent advances of migration tools have accommodated new metrics, the underlying engine is based on the one-dimensional (1D) layout compaction algorithm, largely due to its efficiency compared to its two-dimensional (2D) counterpart. In this paper, we propose a new method that can overcome the artificial constraints introduced by the 1D compaction algorithm, thereby effectively achieving the quality of 2D compaction yet keeping the computational cost almost as low as 1D compaction. Our method is based on the application of soft constraints, or artificial constraints that are initially relaxed, and gradually tightened to be satisfied. We demonstrate the effectiveness of our approach by successfully solving the difficult 1D compaction instances we found in the migration of the Berkeley low power library, originally developed for 1.2 /spl mu/m MOSIS process, into TSMC 0.25 /spl mu/m and 0.18 /spl mu/m technology.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130444131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信