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Sensitivity-based gate delay propagation in static timing analysis 静态时序分析中基于灵敏度的门延迟传播
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.108
Shahin Nazarian, Massoud Pedram, E. Tuncer, Tao Lin
{"title":"Sensitivity-based gate delay propagation in static timing analysis","authors":"Shahin Nazarian, Massoud Pedram, E. Tuncer, Tao Lin","doi":"10.1109/ISQED.2005.108","DOIUrl":"https://doi.org/10.1109/ISQED.2005.108","url":null,"abstract":"The paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Conventional STA tools represent an electrical waveform at the intermediate node of a logic circuit by its arrival time and slope. In general, these two parameters are calculated based on the time instances at which the input waveform passes through predetermined voltage levels. However, to account properly for the impact of noise on the shape of a waveform, it is insufficient to model the waveform using only two parameters. The key contribution of the proposed methodology is to base the timing analysis on the sensitivity of the output waveform to the input waveform and accurately, yet efficiently, propagate equivalent electrical waveforms throughout a VLSI circuit. A hybrid technique combines the sensitivity-based approach with an energy-based technique to increase the efficiency of gate delay propagation. Experimental results demonstrate the higher accuracy of our methodology compared to the best of the existing techniques. The sensitivity-based technique is compatible with the current level of gate characterization in conventional ASIC cell libraries, and so it can be easily incorporated into commercial STA tools to enhance their accuracy.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129804506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low voltage test in place of fast clock in DDSI delay test 低电压测试代替快速时钟在DDSI延迟测试
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.75
Haihua Yan, Gefu Xu, A. Singh
{"title":"Low voltage test in place of fast clock in DDSI delay test","authors":"Haihua Yan, Gefu Xu, A. Singh","doi":"10.1109/ISQED.2005.75","DOIUrl":"https://doi.org/10.1109/ISQED.2005.75","url":null,"abstract":"By testing the CUT at lower supply voltages, the CUT slows down and thus slow, low-cost testers can be used to perform DDSI (defect detection within slack intervals) tests. Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results are presented to investigate the potential of the method.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126438531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC 一个用于验证和改进基于FPGA的高分辨率音频ADC测试策略的协同设计工具
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.3
D. Venuto, Grazia Marchione, L. Reyneri
{"title":"A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC","authors":"D. Venuto, Grazia Marchione, L. Reyneri","doi":"10.1109/ISQED.2005.3","DOIUrl":"https://doi.org/10.1109/ISQED.2005.3","url":null,"abstract":"Results from intensive investigation of a new so-called polynomial fitting method have demonstrated to be a promising technique for fast test of high-resolution ADC. Within this work, a recently developed CodeSimulink HW/SW codesign tool suitable to design, simulate and tune the digital HW required for the proposed method has been employed. The investigations have underlined the limits of the method and also allowed the introduction of possible improvements on the original technique, as shown in the paper.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117228009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Electromigration reliability comparison of Cu and Al interconnects 铜和铝互连的电迁移可靠性比较
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.51
S. Alam, F. Wei, C. Gan, C. Thompson, D. Troxel
{"title":"Electromigration reliability comparison of Cu and Al interconnects","authors":"S. Alam, F. Wei, C. Gan, C. Thompson, D. Troxel","doi":"10.1109/ISQED.2005.51","DOIUrl":"https://doi.org/10.1109/ISQED.2005.51","url":null,"abstract":"Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the interface of the Cu and the inter-level diffusion barrier, such as Si/sub 3/N/sub 4/, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating conditions, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115958948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A more effective C/sub EFF/ 一个更有效的C/sub / EFF/
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.10
S. Nassif, Zhuo Li
{"title":"A more effective C/sub EFF/","authors":"S. Nassif, Zhuo Li","doi":"10.1109/ISQED.2005.10","DOIUrl":"https://doi.org/10.1109/ISQED.2005.10","url":null,"abstract":"Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for drivers with lumped capacitive loads. This necessitates the translation of the actual loading and interconnect parasitics into a single effective capacitance. Existing approaches to perform that translation are either iterative in nature or involve iterative procedure to solve non-closed form equations and thus costly in CPU time. This paper presents a new accurate and simple closed form approach to deal with effective capacitance.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"90 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Testing for resistive shorts in FPGA interconnects FPGA互连中电阻短路的测试
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.120
Haixia Gao, Yintang Yang, Xiao-hua Ma, Gang Dong
{"title":"Testing for resistive shorts in FPGA interconnects","authors":"Haixia Gao, Yintang Yang, Xiao-hua Ma, Gang Dong","doi":"10.1109/ISQED.2005.120","DOIUrl":"https://doi.org/10.1109/ISQED.2005.120","url":null,"abstract":"The behavior of resistive short defects in FPGA interconnects was investigated through simulation and theoretical analysis. These defects cause timing failures and even Boolean faults for small defect resistance values. For large defect resistance values, the best defect situations happen when the path under test makes a v-to-v transition and another path causing short faults remains at value v. Under the best test situations, the effects of supply voltage, temperature and extra loads on test results were evaluated. Lower voltage and lower temperature can improve detectability, but the adding branch technique is not suitable for short defect testing.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132569208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and evaluation of a security scheme for sensor networks 传感器网络安全方案的设计与评估
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.39
Khadija Stewart, T. Haniotakis, S. Tragoudas
{"title":"Design and evaluation of a security scheme for sensor networks","authors":"Khadija Stewart, T. Haniotakis, S. Tragoudas","doi":"10.1109/ISQED.2005.39","DOIUrl":"https://doi.org/10.1109/ISQED.2005.39","url":null,"abstract":"A keyless methodology to ensure secure data transmission in a network of sensors is presented. The main feature is the low power consumption due to the simplicity of the hardware that has to be implemented within each sensor. Experimental results demonstrate that the power dissipation overhead in each sensor's system is minimal when compared to key-based security methods. Experimental evidence of the security features of the presented method is also given.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131444018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Early assessment of leakage power for system level design 泄漏功率的早期评估，为系统级设计提供依据
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.50
C. Talarico, B. Pillilli, K. L. Vakati, Janet M. Wang
{"title":"Early assessment of leakage power for system level design","authors":"C. Talarico, B. Pillilli, K. L. Vakati, Janet M. Wang","doi":"10.1109/ISQED.2005.50","DOIUrl":"https://doi.org/10.1109/ISQED.2005.50","url":null,"abstract":"This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into account the simultaneous effect of threshold-voltage (Vt), oxide thickness (t/sub ox/), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15/spl times/ faster.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122119728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A built-in self-test scheme for differential ring oscillators 一个内置自检方案的差动环振荡器
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.2
L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni
{"title":"A built-in self-test scheme for differential ring oscillators","authors":"L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni","doi":"10.1109/ISQED.2005.2","DOIUrl":"https://doi.org/10.1109/ISQED.2005.2","url":null,"abstract":"In this paper a new built-in self-test (BIST) scheme is proposed suitable for testing differential voltage controlled ring oscillators. The proposed testing-scheme is capable of detecting single realistic faults of the circuit under test. These faults can be either short or bridging faults between circuit nodes or open faults at the circuit branches. The test result is provided by a digital fail/pass indication signal. Exhaustive simulations have revealed the effectiveness of the proposed technique regarding its fault coverage.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116672951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dummy filling methods for reducing interconnect capacitance and number of fills 用于减少互连电容和填充次数的虚拟填充方法
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.47
A. Kurokawa, T. Kanamoto, Tetsuya Ibe, Akira Kasebe, W. F. Chang, T. Kage, Y. Inoue, H. Masuda
{"title":"Dummy filling methods for reducing interconnect capacitance and number of fills","authors":"A. Kurokawa, T. Kanamoto, Tetsuya Ibe, Akira Kasebe, W. F. Chang, T. Kage, Y. Inoue, H. Masuda","doi":"10.1109/ISQED.2005.47","DOIUrl":"https://doi.org/10.1109/ISQED.2005.47","url":null,"abstract":"In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: (1) improved floating square fills, (2) floating parallel lines, and (3) floating perpendicular lines (with spacing between dummy metals above and below signal lines). We also present efficient simple formulas for estimating the appropriate spacing and number of fills. In our experiments, the capacitance increase using the traditional regular square method was 13.1%, while that using the methods of improved square fills, extended parallel lines, and perpendicular lines was 2.5%, 2.4%, and 1.1%, respectively. Moreover, the number of necessary dummy metals can be reduced by two orders of magnitude through use of the parallel line method.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117154558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
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