低电压测试代替快速时钟在DDSI延迟测试

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI:10.1109/ISQED.2005.75

Haihua Yan, Gefu Xu, A. Singh

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引用次数: 2

摘要

通过在较低的电源电压下测试CUT, CUT减慢了速度，因此可以使用低成本的测试器来执行DDSI(在松弛间隔内缺陷检测)测试。除此之外，由于延迟故障大小在DDSI测试中是已知的，因此可以进一步使用该信息来诊断延迟故障背后的导致机制。实验结果验证了该方法的可行性。

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Low voltage test in place of fast clock in DDSI delay test

By testing the CUT at lower supply voltages, the CUT slows down and thus slow, low-cost testers can be used to perform DDSI (defect detection within slack intervals) tests. Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results are presented to investigate the potential of the method.

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Sixth international symposium on quality electronic design (isqed'05)

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