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Sixth international symposium on quality electronic design (isqed'05)最新文献

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Voltage scaling, wire sizing and repeater insertion design rules for wave-pipelined VLSI global interconnect circuits 波浪管道VLSI全球互连电路的电压缩放、导线尺寸和中继器插入设计规则
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.128
Vinita V. Deodhar, Jeffrey A. Davis
{"title":"Voltage scaling, wire sizing and repeater insertion design rules for wave-pipelined VLSI global interconnect circuits","authors":"Vinita V. Deodhar, Jeffrey A. Davis","doi":"10.1109/ISQED.2005.128","DOIUrl":"https://doi.org/10.1109/ISQED.2005.128","url":null,"abstract":"This paper illustrates a method to determine the optimal voltage, wire sizing and repeater insertion design rules for a global wire routing level that uses wave-pipelined interconnect circuits. In order to balance performance, power and area, a throughput-per-energy-area (TPEA) metric is introduced to guide the design of a global wire routing level to achieve maximum throughput (i.e. bit-rate) with optimal utilization of resources. A 180 nm technology case study for a memory bus channel that requires an aggregate throughput of 332.8 Gbit/s illustrates that the optimal TPEA combination of 1 V supply, 6 repeaters per centimeter, a metal thickness to width aspect ratio of 2.5 and metal pitch to width ratio of 3 gives 12 % reduction in dynamic power and over 60 % reduction in wire area as compared to a published interconnect circuit that uses low voltage differential signaling (LVDS).","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115081176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reseeding-based test set embedding with reduced test sequences 基于重播种的测试集约简嵌入方法
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.105
E. Kalligeros, D. Kaseridis, X. Kavousianos, D. Nikolos
{"title":"Reseeding-based test set embedding with reduced test sequences","authors":"E. Kalligeros, D. Kaseridis, X. Kavousianos, D. Nikolos","doi":"10.1109/ISQED.2005.105","DOIUrl":"https://doi.org/10.1109/ISQED.2005.105","url":null,"abstract":"A novel technique for reducing the test sequences of reseeding-based schemes is presented in this paper. The proposed technique is generic and can be applied to test set embedding or mixed-mode schemes based on various TPG. The imposed hardware overhead is very small since it is confined to just one extra bit per seed plus one very small counter in the scheme's control logic, while the test-sequence-length reductions achieved are up to 44.71%. Along with the test-sequence-reduction technique, an efficient seed-selection algorithm for the test-per-clock, LFSR-based, test set embedding case is presented. The proposed algorithm targets the minimization of the selected seed volumes and, combined with the test-sequence-reduction technique, delivers results with fewer seeds and much smaller test sequences than the already proposed approaches.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Controlled-load limited switch dynamic logic circuit 控制负载限制开关动态逻辑电路
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.35
J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye, Richard B. Brown
{"title":"Controlled-load limited switch dynamic logic circuit","authors":"J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye, Richard B. Brown","doi":"10.1109/ISQED.2005.35","DOIUrl":"https://doi.org/10.1109/ISQED.2005.35","url":null,"abstract":"Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128579268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Analysis and optimization of static power considering transition dependency of leakage current in VLSI circuits 考虑泄漏电流过渡依赖性的VLSI电路静态功率分析与优化
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.18
A. Abdollahi, F. Fallah, Massoud Pedram
{"title":"Analysis and optimization of static power considering transition dependency of leakage current in VLSI circuits","authors":"A. Abdollahi, F. Fallah, Massoud Pedram","doi":"10.1109/ISQED.2005.18","DOIUrl":"https://doi.org/10.1109/ISQED.2005.18","url":null,"abstract":"We show that leakage current in VLSI circuits is not only a function of the current state (input combination) of a combinational circuit but also is dependent on the state history (previous input combinations). As an example application of the transition-dependent leakage model, we extend a known technique for calculating and applying the minimum leakage input vector to a combinational circuit in the standby mode to one which calculates and applies a pair of input vectors to initialize the circuit to the minimum leakage configuration.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parametric yield analysis and constrained-based supply voltage optimization 参数良率分析及基于约束的电源电压优化
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.90
R. Rao, K. Agarwal, A. Devgan, K. Nowka, D. Sylvester, Richard B. Brown
{"title":"Parametric yield analysis and constrained-based supply voltage optimization","authors":"R. Rao, K. Agarwal, A. Devgan, K. Nowka, D. Sylvester, Richard B. Brown","doi":"10.1109/ISQED.2005.90","DOIUrl":"https://doi.org/10.1109/ISQED.2005.90","url":null,"abstract":"Parametric yield loss has become a serious concern in leakage dominated technologies. We discuss the impact of leakage on parametric yield and show that leakage can cause yield windows to shrink by imposing a two-sided constraint on the window. We present a mathematical framework for yield estimation under device process variation for given power and frequency constraints. The model is validated against Monte Carlo simulations for an industry process and is shown to have typical error of less than 5%. We then demonstrate the importance of optimal supply voltage selection for yield maximization. We also investigate the sensitivity of parametric yield to applied frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122319847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An ILP formulation for reliability-oriented high-level synthesis 面向可靠性高阶综合的ILP公式
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.15
S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie, W. Hung
{"title":"An ILP formulation for reliability-oriented high-level synthesis","authors":"S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie, W. Hung","doi":"10.1109/ISQED.2005.15","DOIUrl":"https://doi.org/10.1109/ISQED.2005.15","url":null,"abstract":"Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulation for reliability-oriented high-level synthesis that addresses the soft error problem. The proposed approach tries to maximize reliability of the design while observing the bounds on area and performance, and makes use of our reliability characterization of hardware components such as adders and multipliers. We implemented the proposed approach, performed experiments with several example designs, and compared the results with those obtained by a prior proposal. Our results show that incorporating reliability as a first-class metric during high-level synthesis brings significant improvements on the overall design reliability.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130885871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A min-variance iterative method for fast smart dummy feature density assignment in chemical-mechanical polishing 化学机械抛光中快速智能假人特征密度分配的最小方差迭代方法
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.8
Xin Wang, C. Chiang, J. Kawa, Qing Su
{"title":"A min-variance iterative method for fast smart dummy feature density assignment in chemical-mechanical polishing","authors":"Xin Wang, C. Chiang, J. Kawa, Qing Su","doi":"10.1109/ISQED.2005.8","DOIUrl":"https://doi.org/10.1109/ISQED.2005.8","url":null,"abstract":"Dummy feature filling is an efficient approach for reducing wafer-topography variation in chemical-mechanical polishing (CMP), which is the key planarization process in modern VLSI fabrication. In this paper, we present a new min-variance iterative method for fast smart dummy feature density assignment and post-CMP topography variation reduction. This method iteratively selects target areas using an efficient CMP low-pass filter model and a variance-minimizing heuristic, and assigns/removes dummy features accordingly. Because of the efficient usage of the 2D fast Fourier transform (FFT), the computational cost of this new method is close to O(nlog(n)), making it much faster than the existing linear programming method that costs O(n/sup 3/). Numerical experiments show the computational cost of our new method is almost negligible when compared with the LP method and its solution is very close to the optimal solution.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134503048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Optimization of individual well adaptive body biasing (IWABB) using a multiple objective evolutionary algorithm 基于多目标进化算法的单井自适应体偏置优化
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.87
Justin Gregg, Tom W. Chen
{"title":"Optimization of individual well adaptive body biasing (IWABB) using a multiple objective evolutionary algorithm","authors":"Justin Gregg, Tom W. Chen","doi":"10.1109/ISQED.2005.87","DOIUrl":"https://doi.org/10.1109/ISQED.2005.87","url":null,"abstract":"Mitigating the effects process variations on power-frequency distributions can be done by using a system of locally-generated body biases. This system allows for highly localized circuit optimizations with very little overhead in silicon area and routing resources. We present a multiple objective algorithm to find near-optimal configurations of these biases which can be applied during post-fabrication testing. The system can improve an initial yield of 12% to 77%.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133041874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Charge-based core and the model architecture of BSIM5 基于电荷的BSIM5核心及模型体系结构
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.30
Jin He, J. Xi, M. Chan, H. Wan, M. Dunga, B. Heydari, A. Niknejad, C. Hu
{"title":"Charge-based core and the model architecture of BSIM5","authors":"Jin He, J. Xi, M. Chan, H. Wan, M. Dunga, B. Heydari, A. Niknejad, C. Hu","doi":"10.1109/ISQED.2005.30","DOIUrl":"https://doi.org/10.1109/ISQED.2005.30","url":null,"abstract":"The paper outlines the charge-based core and the architecture of the BSIM5 MOSFET model for sub-100 nm CMOS circuit simulation. The BSIM5 model is a continuous, completely symmetric and accurate non charge-sheet based MOS transistor model derived from the basic device physics, including various physics effects. Comparison of the inversion charge between the BSIM5 prediction and self-consistent numerical solution shows good agreement. The demonstration of fully symmetric characteristics of BSIM5, such as channel current and its high-order derivative in the Gummel symmetry test, and charge and trans-capacitances in a SPICE simulation, also implies BSIM5 is the physically symmetric MOSFET model valid for RF-analog circuit simulations.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114951949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Gate-level mitigation techniques for neutron-induced soft error rate 中子诱导软错误率的门级缓解技术
Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.61
H. Singh, D. Sylvester, D. Blaauw
{"title":"Gate-level mitigation techniques for neutron-induced soft error rate","authors":"H. Singh, D. Sylvester, D. Blaauw","doi":"10.1109/ISQED.2005.61","DOIUrl":"https://doi.org/10.1109/ISQED.2005.61","url":null,"abstract":"Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combinational logic chains and investigate techniques to increase circuit robustness in terms of decreasing the probability of upsetting the capturing latch given a particle strike. We show that using a technique of inserting simple cross-coupled inverter pairs on error prone sites, as well as intelligently placing lower V/sub th/ devices and readjusting device width, can increase the robustness by nearly 20% thereby increasing the mean time between soft errors by almost 25%. This technique incurs substantially less overhead than traditional redundancy approaches to mitigating soft errors.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121052654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
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