Testing for resistive shorts in FPGA interconnects

Abstract

The behavior of resistive short defects in FPGA interconnects was investigated through simulation and theoretical analysis. These defects cause timing failures and even Boolean faults for small defect resistance values. For large defect resistance values, the best defect situations happen when the path under test makes a v-to-v transition and another path causing short faults remains at value v. Under the best test situations, the effects of supply voltage, temperature and extra loads on test results were evaluated. Lower voltage and lower temperature can improve detectability, but the adding branch technique is not suitable for short defect testing.