Early assessment of leakage power for system level design

Abstract

This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into account the simultaneous effect of threshold-voltage (Vt), oxide thickness (t/sub ox/), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15/spl times/ faster.