{"title":"片上电感对纳米级集成电路配电网设计的影响","authors":"N. Srivastava, X. Qi, K. Banerjee","doi":"10.1109/ISQED.2005.64","DOIUrl":null,"url":null,"abstract":"This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chip's power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits\",\"authors\":\"N. Srivastava, X. Qi, K. Banerjee\",\"doi\":\"10.1109/ISQED.2005.64\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chip's power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.\",\"PeriodicalId\":333840,\"journal\":{\"name\":\"Sixth international symposium on quality electronic design (isqed'05)\",\"volume\":\"114 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Sixth international symposium on quality electronic design (isqed'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2005.64\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Sixth international symposium on quality electronic design (isqed'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2005.64","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits
This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chip's power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.