Power grid planning for microprocessors and SoCs

Abstract

This paper describes power grid planning methodology for high-performance microprocessors and SoC chips. It shows how to estimate currents from an existing chip to a new chip. The power grid planning and pre-layout simulation becomes important for time to market of chip design. We discuss the current scaling technique and one SoC design example. More details on the methodology can be found in Zhu (2004).