Modeling and design of chip-package interface

Abstract

Summary form only given. Signal integrity (SI) and power integrity are forecast to be paramount issues for future chip and package designs. Larger numbers of IOs, higher frequencies, and tighter noise margins necessitate the merging of the design paradigms for chip IO and package. We shed light on a new chip-package codesign paradigm and all the technologies necessary to enable it. We first discuss parameterized reduced order models accounting for all high frequency SI effects in the package that can be reliably and automatically extracted by field solvers. We then introduce package-aware chip IO planning and placement, which is the key to chip-packaging codesign. Finally, we cover detailed power and signal integrity modeling and optimization in package.