{"title":"采用独立栅极控制的亚50nm双栅极MOSFET的高性能感测放大器设计","authors":"S. Mukhopadhyay, H. Mahmoodi, K. Roy","doi":"10.1109/ISQED.2005.44","DOIUrl":null,"url":null,"abstract":"The double-gate (DG) transistor has emerged as the most promising device for nanoscale circuit design. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50 nm circuits. In this paper, we propose a high-performance sense-amplifier design using independent gate control in symmetric and asymmetric DG devices. The proposed design reduces the sensing delay of the sense amplifier by 30-35% and dynamic power by 10% (at 6 GHz) from the connected gate design.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET\",\"authors\":\"S. Mukhopadhyay, H. Mahmoodi, K. Roy\",\"doi\":\"10.1109/ISQED.2005.44\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The double-gate (DG) transistor has emerged as the most promising device for nanoscale circuit design. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50 nm circuits. In this paper, we propose a high-performance sense-amplifier design using independent gate control in symmetric and asymmetric DG devices. The proposed design reduces the sensing delay of the sense amplifier by 30-35% and dynamic power by 10% (at 6 GHz) from the connected gate design.\",\"PeriodicalId\":333840,\"journal\":{\"name\":\"Sixth international symposium on quality electronic design (isqed'05)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Sixth international symposium on quality electronic design (isqed'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2005.44\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Sixth international symposium on quality electronic design (isqed'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2005.44","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET
The double-gate (DG) transistor has emerged as the most promising device for nanoscale circuit design. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50 nm circuits. In this paper, we propose a high-performance sense-amplifier design using independent gate control in symmetric and asymmetric DG devices. The proposed design reduces the sensing delay of the sense amplifier by 30-35% and dynamic power by 10% (at 6 GHz) from the connected gate design.