P/G pad placement optimization: problem formulation for best IR drop

Abstract

IR drop minimization has become very difficult for non-flip chip packaged designs due to technology shrink and increasing design frequencies. Different constituents of IR drop on a wire-bond chip (where pads are placed at the die-periphery) are "package-ball to bond-pad drop", "bond-pad to internal global power ring drop" and "internal local power ring drop". Optimization equations are developed to minimize IR drop from the lead-finger-frame to the standard cell power rails on the die by placing the P/G pads optimally for a given power network. Further, optimization equations are developed to minimize trace wire length on package for P/G pads drawing highest current. The cost functions in the optimization equations target minimum IR drop for those regions of the chip that are switching at maximum speed. By use of our cost function for optimizing P/G pad placement, results on the representative chip with about 15 million gates and several hard macros show an improvement of 10% to 15% in worst IR drop value for different floorplans (one floorplan with uniform power density, and the other floorplan with maximum power density much higher than the average power density of the design).