Design of sub-90 nm circuits and design methodologies

Abstract

Summary form only given. The tutorial discusses the design challenges of scaled CMOS circuits in sub-90 nm technologies and the design methodologies required in order to produce robust designs with the desired power-performance trade-off. We focus on four major components: design challenges of sub-90 nm CMOS circuits with particular emphasis on the implications of each individual device scaling element on circuit design; design methodologies for implementing robust circuits with desired power performance characteristics; managing leakage power; circuit design in the presence of uncertainty.