Noise library characterization for large capacity static noise analysis tools

Abstract

Noise glitches can cause timing degradation in switching nodes or incorrect transitions in steady-state or "quiet" nodes. These incorrect transitions can propagate through the circuit, and can create functional errors or failures. This paper presents both a method and a practical implementation technique for accurately and efficiently characterizing and modeling the propagation of noise glitches through a cell within an integrated circuit. A characterization methodology is developed to generate noise immunity criteria (NIC) and noise propagation tables (NPT) for a given cell library. The resulting look-up tables are appended to any standard gate-level library to be utilized by static timing and noise analysis (STNA) tools.