发布求助
文献互助 智能选刊 最新文献

Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)最新文献

筛选
英文 中文
CVD TaN barrier for copper metallization and DRAM bottom electrode 铜金属化用CVD TaN阻挡层及DRAM底电极
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787096
A. Paranjpe, R. Bubber, L. Velo, G. Shang, S. Gopinath, J. Dalton, M. Moslehi
{"title":"CVD TaN barrier for copper metallization and DRAM bottom electrode","authors":"A. Paranjpe, R. Bubber, L. Velo, G. Shang, S. Gopinath, J. Dalton, M. Moslehi","doi":"10.1109/IITC.1999.787096","DOIUrl":"https://doi.org/10.1109/IITC.1999.787096","url":null,"abstract":"The extendibility of PVD barriers is expected to become a limiting factor for 0.13 /spl mu/m copper metallization, and an MOCVD barrier is likely to be indispensable due to its superior conformality. A 400/spl deg/C process for deposition of a nanocrystalline conformal (>85%) MOCVD TaN layer in high aspect ratio (AR>5) trenches/vias with barrier properties equivalent to c-PVD TaN has been developed using a liquid organometallic precursor. This enables barrier thickness to be scaled to <125 /spl Aring/ compared to >250 /spl Aring/ for i-PVD TaN. Resistivity of /spl sim/1000 /spl mu//spl Omega/-cm has been achieved, which can be further reduced through barrier engineering. MOCVD TaN is a key enabler for extendibility of copper metallization to the sub-0.13 /spl mu/m technology node.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125322260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Interconnect performance modeling for 3D integrated circuits with multiple Si layers 多硅层三维集成电路互连性能建模
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787067
S. Souri, K. C. Saraswat
{"title":"Interconnect performance modeling for 3D integrated circuits with multiple Si layers","authors":"S. Souri, K. C. Saraswat","doi":"10.1109/IITC.1999.787067","DOIUrl":"https://doi.org/10.1109/IITC.1999.787067","url":null,"abstract":"Long interconnect RC delay is increasing rapidly with chip size, limiting chip performance. 3D device integration in multiple layers of Si promises to increase transistor packing density and reduce RC time delay through reducing chip size. This paper offers a quantitative approach to compare current technology chip performance to that of 3D ICs.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126479161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Highly <111> textured Cu film formation on CVD-TiN film by Ti underlayer and Ar sputter etch for damascene interconnection 利用Ti衬底和Ar溅射蚀刻在CVD-TiN薄膜上形成高度织构的Cu膜，用于damese互连
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787095
M. Sekiguchi, H. Sato, T. Harada, R. Etoh
{"title":"Highly <111> textured Cu film formation on CVD-TiN film by Ti underlayer and Ar sputter etch for damascene interconnection","authors":"M. Sekiguchi, H. Sato, T. Harada, R. Etoh","doi":"10.1109/IITC.1999.787095","DOIUrl":"https://doi.org/10.1109/IITC.1999.787095","url":null,"abstract":"Highly (111)-oriented texture and high wetting of Cu films on\u0000CVD-TiN films are achieved by use of a (002)-oriented sputtered Ti\u0000underlayer and an Ar sputter etch before Ti deposition. This process\u0000enhances (111)-oriented crystallization of the amorphous CVD-TiN film.\u0000As a result, 〈111〉 texture and wetting of Cu films are as same\u0000as those of Cu on Ta films. Cu films with a damascene structure also\u0000show a highly (111)-oriented texture","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121985427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Investigation of Ta, TaN and TaSiN barriers for copper interconnects 铜互连用Ta、TaN和TaSiN阻挡物的研究
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787098
Qing-Tang Jiang, R. Faust, H. Lam, J. Mucha
{"title":"Investigation of Ta, TaN and TaSiN barriers for copper interconnects","authors":"Qing-Tang Jiang, R. Faust, H. Lam, J. Mucha","doi":"10.1109/IITC.1999.787098","DOIUrl":"https://doi.org/10.1109/IITC.1999.787098","url":null,"abstract":"The effects of Ta, TaN, and TaSiN barrier materials on Cu seed layers and subsequent electroplating were investigated. Significant agglomeration of the Cu seed on damascene trench sidewalls was observed after annealing of the seed deposited on Ta and TaN barriers. With TaSiN, a relatively smooth and continuous Cu seed layer was observed both before and after the anneal. XRD studies indicate that Cu-filled damascene lines with TaSiN barriers have the least stress and the strongest (111) texture as compared to Cu-filled lines with Ta and TaN barriers.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133376577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Cu interconnect technologies in Fujitsu and problems in installing Cu equipment in an existing semiconductor manufacturing line 富士通的铜互连技术以及在现有半导体生产线上安装铜设备的问题
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787094
M. Yamada, H. Yagi, S. Sugatani, M. Miyajima, D. Matsunaga, T. Hosoda, H. Kudo, N. Misawa, T. Nakamura
{"title":"Cu interconnect technologies in Fujitsu and problems in installing Cu equipment in an existing semiconductor manufacturing line","authors":"M. Yamada, H. Yagi, S. Sugatani, M. Miyajima, D. Matsunaga, T. Hosoda, H. Kudo, N. Misawa, T. Nakamura","doi":"10.1109/IITC.1999.787094","DOIUrl":"https://doi.org/10.1109/IITC.1999.787094","url":null,"abstract":"Summary form only given. In this paper, Cu interconnect technologies in Fujitsu targeted for the 0.18 /spl mu/m generation and beyond are introduced. Some new integration schemes for Cu wiring are also demonstrated, targeted for the 0.13 /spl mu/m generation. Finally, we discuss some important aspects of installation of Cu equipment in an existing semiconductor manufacturing line.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130145698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of damascene feature fill for copper electroplating process 铜电镀工艺中大马士革特征填料的优化
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787145
J. Reid, V. Bhaskaran, R. Contolini, E. Patton, R. Jackson, E. Broadbent, T. Walsh, S. Mayer, R. Schetty, J. Martin, M. Toben, S. Menard
{"title":"Optimization of damascene feature fill for copper electroplating process","authors":"J. Reid, V. Bhaskaran, R. Contolini, E. Patton, R. Jackson, E. Broadbent, T. Walsh, S. Mayer, R. Schetty, J. Martin, M. Toben, S. Menard","doi":"10.1109/IITC.1999.787145","DOIUrl":"https://doi.org/10.1109/IITC.1999.787145","url":null,"abstract":"A copper electroplating process suitable for routine IC manufacturing use must deliver Cu films that reproducibly fill deep, narrow damascene features. In this paper, several important factors such as seed layer coverage, plating waveform (DC, reversed-pulse), and additive chemistry formulation were examined in terms of their effect on the elimination of localized void defects within filled structures. A combination of two-step DC plating and custom additive chemistry enabling complete fill of 9:1 aspect ratio (AR), 0.13 /spl mu/m trenches and 5:1 AR, 0.18 /spl mu/m vias was accomplished.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125975833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Circuit impact and skew-corner analysis of stochastic process variation in global interconnect 全局互连中随机过程变化的电路冲击和斜角分析
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787130
O. S. Nakagawa, N. Chang, S. Lin, D. Sylvester
{"title":"Circuit impact and skew-corner analysis of stochastic process variation in global interconnect","authors":"O. S. Nakagawa, N. Chang, S. Lin, D. Sylvester","doi":"10.1109/IITC.1999.787130","DOIUrl":"https://doi.org/10.1109/IITC.1999.787130","url":null,"abstract":"This paper details the impact of the stochastic interconnect process variation on the circuit performance of global interconnects in deep-submicron logic chips. Signal delay, rise time, and crosstalk variations of global interconnect circuits were first calculated by Monte Carlo simulations using a finite-difference field solver and a SPICE circuit simulator. These circuit performance matrices were subsequently expressed as a response surface function (RSF) of line width, line thickness, and dielectric thickness. The circuit impact was then gauged by a product of sensitivity obtained from the RSF and standard deviation derived from the manufacturing line. Furthermore, the RSF and the joint probability function (JPF) were combined to efficiently generate statistics-based 3-/spl sigma/ process corners. These process corners significantly improved circuit performance bounds in chip design, as compared to the overly pessimistic, conventional worst-case skew-corners.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116433016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Post etch residue removal: novel dry clean technology using densified fluid cleaning (DFC) 蚀刻后残留去除:采用致密流体清洗(DFC)的新型干法清洁技术
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787102
Dafna Beery, Karen Reinhardt, Patricia B. Smith, Janelle Kelley, Arunthati Sivasothy
{"title":"Post etch residue removal: novel dry clean technology using densified fluid cleaning (DFC)","authors":"Dafna Beery, Karen Reinhardt, Patricia B. Smith, Janelle Kelley, Arunthati Sivasothy","doi":"10.1109/IITC.1999.787102","DOIUrl":"https://doi.org/10.1109/IITC.1999.787102","url":null,"abstract":"A novel dry cleaning technology has been developed by GaSonics, which was successfully applied to post etch residue removal. Densified fluid cleaning (DFC) is a dry source, liquid mode cleaning technology. It is based on application of densified gases at elevated pressures and low temperatures. When used together with microwave downstream plasma treatments, DFC enables the damage-free removal of heavy post etch residues containing Al, Ti or Cu, which are not readily affected by other wafer cleaning methods.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116399875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Overcoming sheet resistance effects to enable electroplating of copper onto seedless barrier films 克服片阻效应，使铜电镀在无籽阻隔膜上
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-26 DOI: 10.1109/IITC.1999.787144
K. Takahashi
{"title":"Overcoming sheet resistance effects to enable electroplating of copper onto seedless barrier films","authors":"K. Takahashi","doi":"10.1109/IITC.1999.787144","DOIUrl":"https://doi.org/10.1109/IITC.1999.787144","url":null,"abstract":"An analytical solution for the metal resistance-controlled plating current distribution on circular wafers is obtained to determine the conditions under which a uniform metal film can be electro-deposited on a resistive film. Results indicate that, when using conventional copper plating solutions, uniform films cannot be deposited on 500 /spl Aring/ thick barrier layers consisting of Ta (or more resistive metals) on 200 mm wafers, regardless of plating current density. Uniformity can be characterized by a dimensionless polarization parameter that reflects the influences of current density and physical and chemical properties. Of these properties, the only one that can be varied enough to allow Cu plating on a barrier film is the plating exchange current density, i/sub o/. By lowering the copper concentration and thus i/sub o/ in the plating bath by one or two orders of magnitude below levels that are commonly employed, a uniform conformal conduction layer can be electro-deposited, subsequently allowing the bulk copper film to be plated at high rates.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"2021 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115134495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
BLO/spl kappa//sup TM/-a low-/spl kappa/ dielectric barrier/etch stop film for copper damascene applications BLO/spl kappa//sup TM/-一种低/spl kappa/介电屏障/蚀刻停止膜，用于铜damascene应用
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787093
Ping Xu, Kegang Huang, A. Patel, S. Rathi, B. Tang, J. Ferguson, J. Huang, C. Ngai, M. Loboda
{"title":"BLO/spl kappa//sup TM/-a low-/spl kappa/ dielectric barrier/etch stop film for copper damascene applications","authors":"Ping Xu, Kegang Huang, A. Patel, S. Rathi, B. Tang, J. Ferguson, J. Huang, C. Ngai, M. Loboda","doi":"10.1109/IITC.1999.787093","DOIUrl":"https://doi.org/10.1109/IITC.1999.787093","url":null,"abstract":"A low-/spl kappa/ dielectric barrier/etch stop film has been developed for use in copper damascene processes. The film is deposited using Dow Corning/sup R/ organosilicon gas as a precursor in a single-wafer PECVD chamber, and has a lower dielectric constant (/spl les/5) compared to the SiC film (>7) generated by SiH/sub 4/ and CH/sub 4/ and plasma silicon nitrides (>7). This film is amorphous and composed of silicon, carbon and hydrogen (a-SiC:H). The film characterization, including physical, electrical, copper diffusion barrier properties, and etch selectivity demonstrated that this film is a good barrier/etch stop for low-/spl kappa/ copper damascene applications. Due to its low dielectric constant, low effective /spl kappa/ values can be achieved in damascene devices. This film has been named BLO/spl kappa//sup TM/ (barrier low /spl kappa/) (Pai and Ting, 1989).","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信