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Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)最新文献

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The investigation of electroplating deposited copper films for advanced VLSI interconnection 先进VLSI互连用电镀铜膜的研究
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787080
H.C. Chen, M.S. Yang, J.Y. Wu, W. Lur
{"title":"The investigation of electroplating deposited copper films for advanced VLSI interconnection","authors":"H.C. Chen, M.S. Yang, J.Y. Wu, W. Lur","doi":"10.1109/IITC.1999.787080","DOIUrl":"https://doi.org/10.1109/IITC.1999.787080","url":null,"abstract":"The characteristics of electroplating deposited (EPD) copper films after annealing are investigated by means of sheet resistance, film hardness, film stress, surface roughness, and the chemical mechanical polishing process. Films annealed at 150/spl deg/C showed very similar behavior to those annealed at room temperature for three days in many aspects, including sheet resistance, hardness, surface morphology, and CMP polish rate. Annealing at temperatures higher than 300/spl deg/C resulted in lower sheet resistance, larger grain size, and rougher surfaces, as well as better CMP performance. Atomic force microscopy showed that the surface was rougher as the annealing temperature increased. Better CMP polish rate and uniformity were obtained on fully recrystallized films. Therefore, post-EPD annealing at about 300/spl deg/C to stabilize the copper films is necessary for better CMP process performance.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127510512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Experimental determination of the importance of inductance in sub-micron microstrip lines 亚微米微带线中电感重要性的实验测定
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787114
R. Friar, D. Neikirk
{"title":"Experimental determination of the importance of inductance in sub-micron microstrip lines","authors":"R. Friar, D. Neikirk","doi":"10.1109/IITC.1999.787114","DOIUrl":"https://doi.org/10.1109/IITC.1999.787114","url":null,"abstract":"The importance of inductance in sub-micron cross-section interconnect lines is examined. We experimentally show that small cross-section, high-loss lines are RC dominated into the low GHz frequency range, and only begin to exhibit inductive effects above 10 GHz. We also show by comparing experimental data and a simple model that the skin effect and substrate effects are small, if present, in these lines up to 40 GHz.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126760558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations 传统Al-W与双镶嵌铜集成电路的过刻变化比较
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787092
B. Smith, S. Blackley, R. Carter, S. Chheda, P. Crabtree, D. Farber, M. Gall, R. Islam, D. Jawarani, C. King, D. Menke, R. Nelson, L. Pressley, D. Smith, T. Sparks, T. Stephens, E. Travis, S. Venkatesan
{"title":"A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations","authors":"B. Smith, S. Blackley, R. Carter, S. Chheda, P. Crabtree, D. Farber, M. Gall, R. Islam, D. Jawarani, C. King, D. Menke, R. Nelson, L. Pressley, D. Smith, T. Sparks, T. Stephens, E. Travis, S. Venkatesan","doi":"10.1109/IITC.1999.787092","DOIUrl":"https://doi.org/10.1109/IITC.1999.787092","url":null,"abstract":"A comparison of via overetch is made between a conventional integration using aluminum interconnects plus tungsten via plugs and a dual-inlaid integration using copper. Excessive overetch for Al interconnects can cause reliability problems because of veil formation, as well as create very high aspect ratio recesses that are difficult to fill. The reasons for variation in interlevel dielectric (ILD) thickness and via etch rate are discussed. For the Al-W interconnect system, oxide CMP controls the ILD thickness. In addition, the via etch rate has been observed to drop over time. Both contribute significant variations to via overetch. For a via-first dual-inlaid integration, the ILD deposition determines the via depth uniformity. In metal-first dual-inlaid, the metal trench etch controls the via depth. In both cases, the via etch rate has been optimized to be more stable over time. Overall, the Al-W integration has a very wide range of via depths and etch rates that must be tolerated, whereas the dual-inlaid integrations have only a few percent of variation.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124629069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analysis of interconnect delay for 0.18 /spl mu/m technology and beyond 0.18 /spl mu/m及以上技术的互连延迟分析
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787081
Shien-Yang Wu, B. Liew, K.L. Young, C. Yu, S.C. Sun
{"title":"Analysis of interconnect delay for 0.18 /spl mu/m technology and beyond","authors":"Shien-Yang Wu, B. Liew, K.L. Young, C. Yu, S.C. Sun","doi":"10.1109/IITC.1999.787081","DOIUrl":"https://doi.org/10.1109/IITC.1999.787081","url":null,"abstract":"In this paper, several interconnect schemes are investigated in terms of RC delay. An inverter ring oscillator with a three-line three-section RC interconnect model is used for this study. It is shown that a dual damascene Cu interconnect with lower k-value anti-diffusion layer such as SiBON (k=3.9) can out-perform Al-based interconnects for the same conductor thickness, when intra- and inter-metal dielectrics of similar k-value are used. In addition, when using Cu with 60% of Al thickness, the dual damascene Cu/USG has better interconnect delay performance than even Al/HSQ for narrow metal spacing. Guidelines for dual damascene Cu interconnect optimization can be obtained through the sensitivity study of interconnect process parameters on RC delay presented here.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126254181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Fluorine effects on silicidation of BF/sub 2//sup +/-implanted narrow poly lines 氟对BF/sub /sup +/-注入窄聚线硅化的影响
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787071
C. W. Yap, S. Siah, E. Lim, T.K. Lee, F. Gn
{"title":"Fluorine effects on silicidation of BF/sub 2//sup +/-implanted narrow poly lines","authors":"C. W. Yap, S. Siah, E. Lim, T.K. Lee, F. Gn","doi":"10.1109/IITC.1999.787071","DOIUrl":"https://doi.org/10.1109/IITC.1999.787071","url":null,"abstract":"The use of BF/sub 2//sup +/ for p/sup +/ source/drain implant has resulted in void formation in TiSi/sub 2/ films on p/sup +/ poly and diffusion regions due to the interaction between fluorine outdiffusion and Ti silicidation. When using B/sup +/ instead of BF/sub 2//sup +/, no voids were observed. Deposition of a TEOS layer (150 /spl Aring/) as a fluorine gettering source before p/sup +/ activation anneal reduces the number of voids formed considerably. The sheet resistance of the silicided p/sup +/ narrow poly has improved substantially with the reduction or elimination of the fluorine-induced effects.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125722785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technology challenges for advanced Cu CMP using a new slurry free process 采用新型无浆工艺的先进Cu CMP的技术挑战
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787088
M. Matsumoto, K. Suzuki, T. Sakamoto, A. Kamisawa
{"title":"Technology challenges for advanced Cu CMP using a new slurry free process","authors":"M. Matsumoto, K. Suzuki, T. Sakamoto, A. Kamisawa","doi":"10.1109/IITC.1999.787088","DOIUrl":"https://doi.org/10.1109/IITC.1999.787088","url":null,"abstract":"We present an advantage, from the viewpoint of simplicity, in designing the chemical reaction mechanism during chemical-mechanical polishing (CMP) with a new slurry-free CMP process (Sethuraman, 1998; Fayolle et al., 1998). Cu-CMP has been widely reported as one of the leading techniques for Cu interconnect applications. Cu CMP, however, involves several issues such as Cu dishing, Cu recess, oxide erosion and oxide rounding (Steigerwald, 1997). We have previously reported the high performance of a new slurry free Cu-CMP (Matsumoto et al., 1998). Although a large number of studies have been made of Cu-CMP, little is known about the chemical reaction mechanism, since the conventional technique using slurry and a porous pad has a complex mechanism, i.e. the cohesion of abrasive particles and chemical reaction. Therefore, to solve these issues, this paper reports the mechanism and performance of a new slurry-free Cu-CMP technique. We conclude that dishing and erosion issues can be solved by means of the chemical approach in a new slurry free Cu-CMP technique.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134309841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fully integrated pillar process for high performance Cu interconnect scheme 一种用于高性能铜互连方案的完全集成的支柱工艺
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787138
A. Kajita, K. Higashi, N. Matsunaga, H. Shibata
{"title":"A fully integrated pillar process for high performance Cu interconnect scheme","authors":"A. Kajita, K. Higashi, N. Matsunaga, H. Shibata","doi":"10.1109/IITC.1999.787138","DOIUrl":"https://doi.org/10.1109/IITC.1999.787138","url":null,"abstract":"A novel back-end of the line process for sub-quarter micron high performance devices, which is called the pillar process, has been proposed. The main features of the process is to form aluminum pillars as via plugs. Compared with the conventional metal plug process, the fine via opening process and complicated cleaning at the via interface are not required. By combining the pillar with a Cu single-damascene process, excellent electrical characteristics such as 20% lower wire resistance and 30% lower via resistance than that of conventional Cu dual-damascene structures have been obtained.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132617265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pulsed plasma CVD of fluorocarbon thin films [low-k ILDs] 碳氟薄膜的脉冲等离子体CVD[低k ILDs]
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787077
C. Labelle, K. Lau, K. Gleason
{"title":"Pulsed plasma CVD of fluorocarbon thin films [low-k ILDs]","authors":"C. Labelle, K. Lau, K. Gleason","doi":"10.1109/IITC.1999.787077","DOIUrl":"https://doi.org/10.1109/IITC.1999.787077","url":null,"abstract":"Pulsed PECVD has been used to deposit a range of fluorocarbon films utilizing three different precursors: hexafluoropropylene oxide (HFPO), 1,1,2,2-tetrafluoroethane (C/sub 2/H/sub 2/F/sub 4/), and difluoromethane (CH/sub 2/F/sub 2/). C-1s XPS shows that films from HFPO are dominated by CF/sub 2/ groups, films from CH/sub 2/F/sub 2/ are dominated by C-CF groups, and films from C/sub 2/H/sub 2/F/sub 4/ have significant concentrations of both groups. Gas-phase FTIR has been used to identify the species in each pulsed plasma effluent and the pulsed plasma chemistry has been inferred from them. Large differences in gas-phase effluent species have been found between the three precursors, and a correlation can be drawn between the dominant reactions in a pulsed plasma and the resulting films. Finally, /sup 19/F and /sup 13/C nuclear magnetic resonance (NMR) spectroscopy has been used to further define the various film structures, and these more detailed structural analyses have been used to correlate specific structural configurations to thermal stability.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117073227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Metal bit-line common contact integration technology in 0.17 /spl mu/m-DRAM and merged DRAM in logic devices 金属位线共接触集成技术在0.17 /spl mu/m-DRAM和逻辑器件中合并DRAM
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787101
Siyoung Choi, B. Yoo, Jae-Hak Kim, Seungwook Choi, Hyeon-deok Lee, Ho-Kyu Kang, Yong Park, Jongwoo Park, Moonyong Lee
{"title":"Metal bit-line common contact integration technology in 0.17 /spl mu/m-DRAM and merged DRAM in logic devices","authors":"Siyoung Choi, B. Yoo, Jae-Hak Kim, Seungwook Choi, Hyeon-deok Lee, Ho-Kyu Kang, Yong Park, Jongwoo Park, Moonyong Lee","doi":"10.1109/IITC.1999.787101","DOIUrl":"https://doi.org/10.1109/IITC.1999.787101","url":null,"abstract":"The metal bit-line common contact (MBCC) process has been successfully integrated in 0.17 /spl mu/m DRAM and in merged DRAM in logic devices. By introducing in-situ i-PVD Ti-TiN on W-plug MBCC, reliable electrical performance, P/sup +/ R/sub c/<1000 /spl Omega//cnt and N/sup +/ R/sub c/<500 /spl Omega//cnt without leakage, and process stability are achieved after thermal treatment at 750/spl deg/C for 100 min.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129479121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scaling effect on electromigration in on-chip Cu wiring 片上铜布线中电迁移的尺度效应
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787140
C. Hu, R. Rosenberg, H. Rathore, D. Nguyen, B. Agarwala
{"title":"Scaling effect on electromigration in on-chip Cu wiring","authors":"C. Hu, R. Rosenberg, H. Rathore, D. Nguyen, B. Agarwala","doi":"10.1109/IITC.1999.787140","DOIUrl":"https://doi.org/10.1109/IITC.1999.787140","url":null,"abstract":"Electromigration in on-chip plated Cu damascene interconnections has been investigated for metal line widths from 0.24 /spl mu/m to 1.3 /spl mu/m. Void growth at the cathode end and protrusions at the anode end of the lines have been found to be the main causes of failure. The failure lifetime was found to decrease linearly with decrease in the cross-sectional area of the line. This behavior can be explained by interface diffusion as the dominant path for transport and by the bamboo-like nature of the microstructure. The factor of n for the lifetime dependence on current density for 0.28 /spl mu/m wide lines, /spl tau/=/spl tau//sub 0/j/sup -n/, was found to increase from 1 to 2 as j increased beyond 25 mA//spl mu/m/sup 2/.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126096180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
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