A fully integrated pillar process for high performance Cu interconnect scheme

A. Kajita, K. Higashi, N. Matsunaga, H. Shibata
{"title":"A fully integrated pillar process for high performance Cu interconnect scheme","authors":"A. Kajita, K. Higashi, N. Matsunaga, H. Shibata","doi":"10.1109/IITC.1999.787138","DOIUrl":null,"url":null,"abstract":"A novel back-end of the line process for sub-quarter micron high performance devices, which is called the pillar process, has been proposed. The main features of the process is to form aluminum pillars as via plugs. Compared with the conventional metal plug process, the fine via opening process and complicated cleaning at the via interface are not required. By combining the pillar with a Cu single-damascene process, excellent electrical characteristics such as 20% lower wire resistance and 30% lower via resistance than that of conventional Cu dual-damascene structures have been obtained.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.1999.787138","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

A novel back-end of the line process for sub-quarter micron high performance devices, which is called the pillar process, has been proposed. The main features of the process is to form aluminum pillars as via plugs. Compared with the conventional metal plug process, the fine via opening process and complicated cleaning at the via interface are not required. By combining the pillar with a Cu single-damascene process, excellent electrical characteristics such as 20% lower wire resistance and 30% lower via resistance than that of conventional Cu dual-damascene structures have been obtained.
一种用于高性能铜互连方案的完全集成的支柱工艺
提出了一种新型的亚四分之一微米高性能器件的后端工艺——柱式工艺。该工艺的主要特点是形成铝柱通过插头。与传统的金属塞工艺相比,不需要精细的开孔工艺和复杂的孔界面清洗。通过将该柱与铜单damascene工艺相结合,获得了比传统铜双damascene结构低20%的导线电阻和30%的通孔电阻等优异的电学特性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信