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Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)最新文献

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Copper CMP integration and time dependent pattern effect 铜CMP集成和时间依赖模式效应
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787110
J. T. Pan, Ping Li, K. Wijekoon, Stan D. Tsai, Fritz Redeker
{"title":"Copper CMP integration and time dependent pattern effect","authors":"J. T. Pan, Ping Li, K. Wijekoon, Stan D. Tsai, Fritz Redeker","doi":"10.1109/IITC.1999.787110","DOIUrl":"https://doi.org/10.1109/IITC.1999.787110","url":null,"abstract":"Pattern dependent copper dishing and oxide erosion have been characterized as a function of overpolishing. Copper thickness loss is the sum of field oxide loss, local oxide erosion, and copper dishing, and all of them increase with the degree of overpolishing. Good agreement was obtained between electrically measured copper thickness and that obtained from physical metrology tools. Copper thickness loss as a function of overpolish was quantified for several structures.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122416856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
High frequency modeling of interconnects in deep-submicron technologies 深亚微米互连技术的高频建模
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787082
C. Cregut, G. Le Carval, J. Chilo
{"title":"High frequency modeling of interconnects in deep-submicron technologies","authors":"C. Cregut, G. Le Carval, J. Chilo","doi":"10.1109/IITC.1999.787082","DOIUrl":"https://doi.org/10.1109/IITC.1999.787082","url":null,"abstract":"In this paper, we evaluate the suitable level of modeling for interconnects in deep sub-micron circuits. We propose high frequency models for transmission lines and crosstalk. Our method is based on the association of electromagnetic (EM) and electrical simulations. We validate the principle of this method by comparisons with time domain characterizations. In particular, we analyze the role of the ground configuration in the mechanisms of crosstalk.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133338421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Influence of sidewall roughness on the reliability of 0.20-/spl mu/m Al RIE wiring 侧壁粗糙度对0.20-/spl mu/m Al - RIE接线可靠性的影响
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787104
R. Ravikumar, H. Cichy, Ronald G. Filippi, E. Kiewra, David L. Rath, G. Stojakovic
{"title":"Influence of sidewall roughness on the reliability of 0.20-/spl mu/m Al RIE wiring","authors":"R. Ravikumar, H. Cichy, Ronald G. Filippi, E. Kiewra, David L. Rath, G. Stojakovic","doi":"10.1109/IITC.1999.787104","DOIUrl":"https://doi.org/10.1109/IITC.1999.787104","url":null,"abstract":"Aluminum based wiring is widely used in the back-end-of-line (BEOL) metallization of integrated circuits. In a 256 Mb dynamic random access memory (DRAM) product, the first level of Al wiring exists at a 0.20 /spl mu/m ground rule. Performance and reliability issues from these aggressive ground rules result in serious challenges for semiconductor fabrication processing at the BEOL. This paper compares two different sidewall roughness profiles which were created by varying the post-metal etch wet clean. The resulting \"rough\" and \"smooth\" sidewall profiles are correlated with the electrical performance and reliability characteristics of the 256 Mb-DRAM product.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132190343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intrinsic electrical properties of Cu/low-k interconnection Cu/低k互连的本征电学性质
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787113
G. Bersuker, V. Blaschke, D. Pekker, D. Wick
{"title":"Intrinsic electrical properties of Cu/low-k interconnection","authors":"G. Bersuker, V. Blaschke, D. Pekker, D. Wick","doi":"10.1109/IITC.1999.787113","DOIUrl":"https://doi.org/10.1109/IITC.1999.787113","url":null,"abstract":"Electrical characterization of Cu/low-k ILD structures was performed to address intrinsic material properties. It was shown that ionic conduction due to contamination inherent to the dielectric was the leading cause of an intrinsic intra-metal line leakage current at low temperatures, while at elevated temperatures, a contribution from electron current was detected. Dielectric and barrier layer parameters that control the conduction process were evaluated.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134121294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electromigration early failure distribution in submicron interconnects 亚微米互连电迁移早期失效分布
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787141
M. Gall, P. Ho, C. Capasso, D. Jawarani, R. Hernandez, H. Kawasaki
{"title":"Electromigration early failure distribution in submicron interconnects","authors":"M. Gall, P. Ho, C. Capasso, D. Jawarani, R. Hernandez, H. Kawasaki","doi":"10.1109/IITC.1999.787141","DOIUrl":"https://doi.org/10.1109/IITC.1999.787141","url":null,"abstract":"The early failure issue in electromigration (EM) has been an unresolved subject of study over the last several decades. A satisfying experimental approach for the detection and analysis of early failures has not yet been established. In this study, a new technique utilizing large interconnect arrays in conjunction with the well-known Wheatstone bridge is presented. A total of more than 20,000 interconnects were tested. The results indicate that the EM failure mechanism studied here follows log-normal behaviour down to the 4 sigma level.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
PVD aluminum dual damascene interconnection: yield comparison between counterbore and self aligned approaches PVD铝双大马士革互连:顶孔和自对准方法之间的产量比较
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787126
A. Blosse, U. Raghuram, S. Thekdi, B. Koutny, G. Lau, S.L. Koh, C. Goodenough, T. Pouedras, A. Sethuraman, S. Geha, T. Chowdhury, S. Guggilla, N. Krishna, J. Su, C. Cha, G. Yao, J. Price
{"title":"PVD aluminum dual damascene interconnection: yield comparison between counterbore and self aligned approaches","authors":"A. Blosse, U. Raghuram, S. Thekdi, B. Koutny, G. Lau, S.L. Koh, C. Goodenough, T. Pouedras, A. Sethuraman, S. Geha, T. Chowdhury, S. Guggilla, N. Krishna, J. Su, C. Cha, G. Yao, J. Price","doi":"10.1109/IITC.1999.787126","DOIUrl":"https://doi.org/10.1109/IITC.1999.787126","url":null,"abstract":"A comparative study of the counterbore dual damascene (CBDD) and self-aligned dual damascene (SADD) approaches with aluminum interconnects was carried out for application to 0.18 /spl mu/m ULSI multilevel interconnects. It is shown that the defect density is lower with the SADD approach. Yield degradation with the CBDD approach is explained by photoresist residues in the bottom of vias, which are difficult to remove due to the high aspect ratio of the holes. The Al-CMP process was optimized by introducing dummy structures to reduce Al dishing on wide interconnect lines. Equivalent yield was demonstrated with the SADD approach in comparison with the standard subtractive aluminum etch process on 0.25 /spl mu/m SRAM technology.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123118696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low k adhesion issues in Cu/low k integration Cu/低k集成中的低k粘附问题
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787109
S. Allada
{"title":"Low k adhesion issues in Cu/low k integration","authors":"S. Allada","doi":"10.1109/IITC.1999.787109","DOIUrl":"https://doi.org/10.1109/IITC.1999.787109","url":null,"abstract":"Adhesion issues at different low k interfaces cause delamination during the copper CMP process. Delamination leads to other issues such as metal thinning, dielectric thinning and scratching. Critical fracture energy (K/sub c/) between substrate and low k and between low k and cap oxide have been investigated. Process optimizations of the spin coating and curing steps will improve substrate adhesion. A statistically-designed experiment was used to identify and isolate the factors affecting cap adhesion and was used to optimize cap adhesion.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123253602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Step like degradation profile of electromigration of W-plug contact w型插头触点电迁移的阶跃退化曲线
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787073
Guo Qiang, L. Foo, Zeng Xu, Neo Soh Ping, Yao Pei, Oh Chong Khiam
{"title":"Step like degradation profile of electromigration of W-plug contact","authors":"Guo Qiang, L. Foo, Zeng Xu, Neo Soh Ping, Yao Pei, Oh Chong Khiam","doi":"10.1109/IITC.1999.787073","DOIUrl":"https://doi.org/10.1109/IITC.1999.787073","url":null,"abstract":"The electromigration (EM) of a W-plug contact to silicon has been investigated by high resolution resistance measurement (HRRM). Step-like resistance degradation curves was observed in EM tests. Scanning electron microscope (SEM) observation shows that the number of voids observed in the Al stripe has a good correlation with that of steps in the degradation profile. A new model was developed to associate the microstructure change to the resistance variation. It was found that each step corresponds to one void completely severing the line. We also showed that the interfacial diffusion is a dominant mechanism of bamboo structures in EM measurements.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low redeposition rate high density plasma CVD process for high aspect ratio 175 nm technology and beyond 低再沉积率高密度等离子体CVD工艺高纵横比175纳米及以上的技术
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787106
G.Y. Lee, T. Ivers, G. Papasouliotis, E. Kiewra, X. Ning, B. van Schravendijk
{"title":"A low redeposition rate high density plasma CVD process for high aspect ratio 175 nm technology and beyond","authors":"G.Y. Lee, T. Ivers, G. Papasouliotis, E. Kiewra, X. Ning, B. van Schravendijk","doi":"10.1109/IITC.1999.787106","DOIUrl":"https://doi.org/10.1109/IITC.1999.787106","url":null,"abstract":"As aluminum reactive ion etch (RIE) technology extends to sub-0.20 /spl mu/m technology, a void-free back-end-of-line (BEOL) gap-fill process is one of the major challenges for interconnects. When a stitched word line architecture is employed, the first metal wiring level often follows the minimum ground rule (GR). To maintain low sheet resistance, the aluminum line height cannot be significantly reduced. Therefore, the aspect ratio of current spaces is well over 2.5 and will approach 4.5 with future lithography shrinkages. Deposition temperature constraints make BEOL gap-fill much harder than front-end-of-line (FEOL), where such high aspect ratios are routinely filled. In this paper, a low redeposition rate high density plasma chemical vapor deposition (HDP-CVD) process has been developed at low deposition temperature to fill beyond 3.0 to 1 aspect ratio without void formation.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124015705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electromigration simulation under DC/AC stresses considering microstructure 考虑微观结构的直流/交流应力下电迁移模拟
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787072
Wei Zhang, J. Bernstein
{"title":"Electromigration simulation under DC/AC stresses considering microstructure","authors":"Wei Zhang, J. Bernstein","doi":"10.1109/IITC.1999.787072","DOIUrl":"https://doi.org/10.1109/IITC.1999.787072","url":null,"abstract":"In this work, we present a dynamic finite difference simulation on the stress evolution along an IC interconnect under both DC and AC current densities, while taking into account the inhomogeneity of grain size and grain boundary orientation. Furthermore, we related both the accelerating stress and microstructural conditions to the lifetime by assuming certain built-up stress levels as failure criteria.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125907488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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