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Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)最新文献

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Damascene process induced charging damage phenomenon 大马士革工艺诱发充装损伤现象
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1999-05-24 DOI: 10.1109/IITC.1999.787143
N. Matsunaga, H. Yoshinari, K. Tomioka, H. Shibata
{"title":"Damascene process induced charging damage phenomenon","authors":"N. Matsunaga, H. Yoshinari, K. Tomioka, H. Shibata","doi":"10.1109/IITC.1999.787143","DOIUrl":"https://doi.org/10.1109/IITC.1999.787143","url":null,"abstract":"Performance degradation of MOSFETs due to plasma charging damage in a damascene interconnect process was evaluated in contrast to the conventional interconnect process which utilizes reactive ion etching (RIE) for metal patterning. Greater MOSFET performance degradation was observed in the damascene interconnect process than that in the metal RIE based interconnect process, notwithstanding the process where devices were directly exposed to plasma was reduced. It is considered that the degradation is due to the discharge current of charges which are charged up in the interconnect trench during the trench RIE process. A two step etching process using an etch stopper on metal was confirmed to reduce the charging damage.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"123 21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116940122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A high aspect ratio sub 0.2 micron Al plug technology for 0.13 /spl mu/m generation 高纵横比低于0.2微米的铝插头技术，可实现0.13 /spl mu/m代
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1900-01-01 DOI: 10.1109/IITC.1999.787124
Tsung-Ju Yang, T. Ku, Tze-Liang Lee, B. Tsui, Lai-Juh Chen, C. Hsia
{"title":"A high aspect ratio sub 0.2 micron Al plug technology for 0.13 /spl mu/m generation","authors":"Tsung-Ju Yang, T. Ku, Tze-Liang Lee, B. Tsui, Lai-Juh Chen, C. Hsia","doi":"10.1109/IITC.1999.787124","DOIUrl":"https://doi.org/10.1109/IITC.1999.787124","url":null,"abstract":"This paper describes a sub-0.2 /spl mu/m Al plug technology with aspect ratio higher than 4 by a two-step cold/hot sputtering using a long-throw sputtering PVD cluster tool for the first time. The key factors for excellent filling, including wetting capability of Ti and TiN/sub x/, cold Al coverage, hot Al temperature and deposition rate have been investigated. Low via resistance (7.5 /spl Omega//via for 0.2 /spl mu/m vias) and high via chain yield (100% for 10K vias) have been achieved using this technology.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126583555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Material property characterization and integration issues for mesoporous silica 介孔二氧化硅材料性能表征及集成问题
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1900-01-01 DOI: 10.1109/IITC.1999.787117
E. T. Ryan, H. Ho, Wen-Li Wu, P. Ho, D. Gidley, J. Drage
{"title":"Material property characterization and integration issues for mesoporous silica","authors":"E. T. Ryan, H. Ho, Wen-Li Wu, P. Ho, D. Gidley, J. Drage","doi":"10.1109/IITC.1999.787117","DOIUrl":"https://doi.org/10.1109/IITC.1999.787117","url":null,"abstract":"SEMATECH is driving the development of new characterization methodologies that are applicable to mesoporous materials. The results from the characterization of AlliedSignal's first xerogel material (Nanoglass K2.2-A10B) illustrate the capabilities of these techniques. The characterization results, together with single-level metal Cu/damascene integration studies, demonstrate the issues involved with these potential ultra-low k materials.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132140974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Critical issues in the integration of copper and low-k dielectrics 铜和低k介电体集成中的关键问题
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1900-01-01 DOI: 10.1109/IITC.1999.787139
R. Donaton, B. Coenagrachts, K. Maex, H. Struyf, S. Vanhaelemeersch, G. Beyer, E. Richard, I. Vervoort, W. Fyen, J. Grillaert, S. van der Groen, M. Stucchi, D. de Roest
{"title":"Critical issues in the integration of copper and low-k dielectrics","authors":"R. Donaton, B. Coenagrachts, K. Maex, H. Struyf, S. Vanhaelemeersch, G. Beyer, E. Richard, I. Vervoort, W. Fyen, J. Grillaert, S. van der Groen, M. Stucchi, D. de Roest","doi":"10.1109/IITC.1999.787139","DOIUrl":"https://doi.org/10.1109/IITC.1999.787139","url":null,"abstract":"Single and dual damascene Cu/low k processes are evaluated. Critical integration issues are discussed. Good Cu continuity is obtained over long meanders. The via resistance in dual damascene structures is optimized and the values obtained are almost three times lower than those achieved for a conventional Al/W metallization process. The interline capacitance was evaluated for various etch and strip procedures. The effect of the Cu/low k process on a front end of line 0.25 /spl mu/m n-MOS process is investigated. The metallization process does not affect the performance of either transistors or field transistors.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"740 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123863063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Non-correlated behavior of sheet resistance and stress during self-annealing of electroplated copper 电镀铜自退火过程中片电阻与应力的非相关行为
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1900-01-01 DOI: 10.1109/IITC.1999.787147
H. Brongersma, I. Vervoort, M. Judelwicz, H. Bender, T. Conard, W. Vandervorst, G. Beyer, E. Richard, R. Palmans, S. Lagrange, K. Maex
{"title":"Non-correlated behavior of sheet resistance and stress during self-annealing of electroplated copper","authors":"H. Brongersma, I. Vervoort, M. Judelwicz, H. Bender, T. Conard, W. Vandervorst, G. Beyer, E. Richard, R. Palmans, S. Lagrange, K. Maex","doi":"10.1109/IITC.1999.787147","DOIUrl":"https://doi.org/10.1109/IITC.1999.787147","url":null,"abstract":"A study of the sheet resistance and stress of electrochemically deposited (ECD) blanket copper layers on a TaN barrier shows that the time dependence of these two parameters are not necessarily the same. This indicates that they are not simply interconnected through the grain size distribution changes occurring at room temperature. The plating bath composition and the resulting contaminant incorporation in the Cu layer during ECD has been identified as an additional important parameter in the explanation of the self-annealing behavior.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116519097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Impact of substrate resistivity on the high frequency performance of metal interconnect 衬底电阻率对金属互连高频性能的影响
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1900-01-01 DOI: 10.1109/IITC.1999.787133
S. Jenei, V. Kol'dyaev, S. Decoutere, R. Kuhn, L. Deferm
{"title":"Impact of substrate resistivity on the high frequency performance of metal interconnect","authors":"S. Jenei, V. Kol'dyaev, S. Decoutere, R. Kuhn, L. Deferm","doi":"10.1109/IITC.1999.787133","DOIUrl":"https://doi.org/10.1109/IITC.1999.787133","url":null,"abstract":"Substrate effects have a major impact on the high frequency performance of interconnects. This paper discusses the impact of the substrate resistivity on the frequency dependence of the intermetal capacitance and mutual inductance, and on the effective metal resistance. The relative importance of this frequency dependence is discussed. As an example, the significance of these effects for on-chip spiral inductors are also demonstrated.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126250283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-k materials etch and strip optimization for sub 0.25 /spl mu/m technology 低钾材料蚀刻和条带优化低于0.25 /spl μ m技术
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1900-01-01 DOI: 10.1109/IITC.1999.787076
T. Gao, W. D. Gray, M. Van Hove, E. Rosseel, H. Struyf, H. Meynen, S. Vanhaelemeersch, K. Maex
{"title":"Low-k materials etch and strip optimization for sub 0.25 /spl mu/m technology","authors":"T. Gao, W. D. Gray, M. Van Hove, E. Rosseel, H. Struyf, H. Meynen, S. Vanhaelemeersch, K. Maex","doi":"10.1109/IITC.1999.787076","DOIUrl":"https://doi.org/10.1109/IITC.1999.787076","url":null,"abstract":"With the introduction of low-k materials into the intermetal dielectric (IMD) layers, it is important to optimize the via etch process in order to minimize the IMD degradation that is caused by harsh O/sub 2/ and wet stripping treatments. A simple, sensitive, and cost-effective measurement method is introduced for the determination of low-k material degradation caused during the via etch process. By using a single damascene comb structure, a large sidewall area of low-k material can be exposed to the etch strip process in question. The intra-line capacitance between the trenches is an extremely sensitive parameter to evaluate material degradation. Using this method, etch and strip processes can be tailored for a specific low-k material, which in turn, improve the interconnect performance and via yield. The results from this method are identical to results coming from the optimization of electrical performance with completely integrated chips and is in very good agreement with FTIR analysis for bare films.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121890801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New effect of Ti-capping layer in Co salicide process promising for deep sub-quarter micron technology 钛盖层在钴盐化工艺中的新效果有望用于深亚四分之一微米工艺
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Pub Date : 1900-01-01 DOI: 10.1109/IITC.1999.787137
J. Ku, Chul-Sung Kim, C.-J. Choi, K. Fujihara, Ho-Kyu Kang, Moon-Yong Lee, J. Chung, eung-Joon Lee, Jang-eun Lee, D. Ko
{"title":"New effect of Ti-capping layer in Co salicide process promising for deep sub-quarter micron technology","authors":"J. Ku, Chul-Sung Kim, C.-J. Choi, K. Fujihara, Ho-Kyu Kang, Moon-Yong Lee, J. Chung, eung-Joon Lee, Jang-eun Lee, D. Ko","doi":"10.1109/IITC.1999.787137","DOIUrl":"https://doi.org/10.1109/IITC.1999.787137","url":null,"abstract":"A new effect of the titanium (Ti) capping layer on cobalt (Co) silicide formation, which is promising for salicidation applications in deep sub-quarter micron devices, was investigated. TEM, SIMS, and XRD data suggest that Ti on top of the cobalt layer diffuses into the Co/Si interface and dissociates the thin silicon oxide at the interface during RTA. As a result, with a Co/Ti process, the sensitivity of Co salicide processes to surface conditions could be minimized, which gives a larger process window to fabricate deep sub-quarter micron devices.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"35 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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