Metal bit-line common contact integration technology in 0.17 /spl mu/m-DRAM and merged DRAM in logic devices

Siyoung Choi, B. Yoo, Jae-Hak Kim, Seungwook Choi, Hyeon-deok Lee, Ho-Kyu Kang, Yong Park, Jongwoo Park, Moonyong Lee
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引用次数: 0

Abstract

The metal bit-line common contact (MBCC) process has been successfully integrated in 0.17 /spl mu/m DRAM and in merged DRAM in logic devices. By introducing in-situ i-PVD Ti-TiN on W-plug MBCC, reliable electrical performance, P/sup +/ R/sub c/<1000 /spl Omega//cnt and N/sup +/ R/sub c/<500 /spl Omega//cnt without leakage, and process stability are achieved after thermal treatment at 750/spl deg/C for 100 min.
金属位线共接触集成技术在0.17 /spl mu/m-DRAM和逻辑器件中合并DRAM
金属位线共接触(MBCC)工艺已成功集成在0.17 /spl mu/m DRAM和逻辑器件的合并DRAM中。通过在w插头MBCC上引入原位i-PVD Ti-TiN,获得了可靠的电气性能,P/sup +/ R/sub c/<1000 /spl ω //cnt和N/sup +/ R/sub c/<500 /spl ω //cnt,在750/spl℃下热处理100 min后无泄漏,工艺稳定。
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