{"title":"多硅层三维集成电路互连性能建模","authors":"S. Souri, K. C. Saraswat","doi":"10.1109/IITC.1999.787067","DOIUrl":null,"url":null,"abstract":"Long interconnect RC delay is increasing rapidly with chip size, limiting chip performance. 3D device integration in multiple layers of Si promises to increase transistor packing density and reduce RC time delay through reducing chip size. This paper offers a quantitative approach to compare current technology chip performance to that of 3D ICs.","PeriodicalId":319568,"journal":{"name":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"Interconnect performance modeling for 3D integrated circuits with multiple Si layers\",\"authors\":\"S. Souri, K. C. Saraswat\",\"doi\":\"10.1109/IITC.1999.787067\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Long interconnect RC delay is increasing rapidly with chip size, limiting chip performance. 3D device integration in multiple layers of Si promises to increase transistor packing density and reduce RC time delay through reducing chip size. This paper offers a quantitative approach to compare current technology chip performance to that of 3D ICs.\",\"PeriodicalId\":319568,\"journal\":{\"name\":\"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)\",\"volume\":\"57 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.1999.787067\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.1999.787067","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Interconnect performance modeling for 3D integrated circuits with multiple Si layers
Long interconnect RC delay is increasing rapidly with chip size, limiting chip performance. 3D device integration in multiple layers of Si promises to increase transistor packing density and reduce RC time delay through reducing chip size. This paper offers a quantitative approach to compare current technology chip performance to that of 3D ICs.