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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC 一种数据速率高达15Gb/s的HBM低电压区域高效TSV I/O，具有重叠复用驱动、ISI补偿器和QEC
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185328
Taeryeong Kim, Ji-Young Kim, J. You, Hohyun Chae, B. Moon, Kyomin Sohn, Seong-ook Jung
{"title":"A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC","authors":"Taeryeong Kim, Ji-Young Kim, J. You, Hohyun Chae, B. Moon, Kyomin Sohn, Seong-ook Jung","doi":"10.23919/VLSITechnologyandCir57934.2023.10185328","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185328","url":null,"abstract":"This paper presents a low-voltage area-efficient through-silicon via (TSV) I/O for the high-bandwidth memory utilizing overlapped multiplexing driver, ISI compensators (hybrid equalizer, direct feedback 1-tap DFE) and quadrature error corrector. The proposed TSV I/O is implemented in 65nm CMOS process with emulated 12-stacked TSV. Measurement results show energy efficiency of 0.145pJ/b/pF and 30% timing margin with BER $lt 10 ^{-12}$ at 15Gb/s with PRBS-31.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133966305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture ffet、混合CMOS逻辑和模拟RRAM阵列的单片3D集成，用于节能可重构内存计算架构
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185221
Yiwei Du, Jianshi Tang, Yijun Li, Yue Xi, B. Gao, H. Qian, Huaqiang Wu
{"title":"Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture","authors":"Yiwei Du, Jianshi Tang, Yijun Li, Yue Xi, B. Gao, H. Qian, Huaqiang Wu","doi":"10.23919/VLSITechnologyandCir57934.2023.10185221","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185221","url":null,"abstract":"In this work, we report a monolithically 3D integration of HfZrOx (HZO) ferroelectric FET (FeFET), analog computing-in-memory (CIM), hybrid back-end-of-line (BEOL) CMOS on top of standard Si-CMOS technology, namely M3D-FACT. The 1st layer is Si CMOS circuits for control logic, and the 2nd layer is an analog resistive random-access memory (RRAM) array for CIM. The 3rd layer is a reconfigurable datapath (RCD), consisting of FeFETs with InGaZnOx (IGZO) channel and hybrid CMOS logic based on carbon nanotube (CNT) PMOS and IGZO NMOS. The structure and functions of each layer were verified. Furthermore, a reconfigurable CIM architecture was implemented using the M3D-FACT chip, and the system-level benchmark against its 2D counterpart shows higher energy efficiency in three different network models (6.9$times $ for VGG-8, 19.2$times$ for DenseNet-121, and 9.9$times$ for ResNet-18).","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"406 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122945940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design 自参考设计不可知激光电压探测攻击检测与100%的保护覆盖率，58%的区域开销自动化设计
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185360
Hui Zhang, Longyang Lin, Qiang Fang, U. Kalingage, M. Alioto
{"title":"Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design","authors":"Hui Zhang, Longyang Lin, Qiang Fang, U. Kalingage, M. Alioto","doi":"10.23919/VLSITechnologyandCir57934.2023.10185360","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185360","url":null,"abstract":"A self-referenced distributed on-chip scheme is introduced to achieve continuous detection of laser voltage probing (LVP) attacks against digital IPs with full-area coverage via temperature sensing. Calibration-free, automated and design-agnostic adoption are enabled by a stdcell-based approach, offering a 2.5X area overhead reduction compared to prior art.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demonstration of crystalline IGZO transistor with high thermal stability for memory applications 用于存储器应用的高热稳定性晶体IGZO晶体管的演示
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185258
Whayoung Kim, Jaehyeong Kim, D. Ko, Jun-Hwe Cha, Gyeongcheol Park, Y. Ahn, Jong-Young Lee, Minchul Sung, Hyejung Choi, S. Ryu, Seiyon Kim, Myung-Hee Na, Seonyong Cha
{"title":"Demonstration of crystalline IGZO transistor with high thermal stability for memory applications","authors":"Whayoung Kim, Jaehyeong Kim, D. Ko, Jun-Hwe Cha, Gyeongcheol Park, Y. Ahn, Jong-Young Lee, Minchul Sung, Hyejung Choi, S. Ryu, Seiyon Kim, Myung-Hee Na, Seonyong Cha","doi":"10.23919/VLSITechnologyandCir57934.2023.10185258","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185258","url":null,"abstract":"Highly ordered crystalline InGaZnO (c-IGZO) TFTs have been demonstrated in subsequent processes above 550 °C compatible with memory applications. Notably, c-IGZO featured strong immunity to high temperature and hydrogen-containing processes unlike amorphous IGZO (a-IGZO) where agglomeration occurs. The c-IGZO TFTs with optimized process in this study show a higher on-current ($mathrm{I}_{mathrm{o}mathrm{n}}$) at a similar $mathrm{V}_{mathrm{t}mathrm{h}}$ of −1 V, and $mathrm{I}_{mathrm{off}}$ of $1.82times 10^{-18}$ A/$mu$m compared with a-IGZO TFTs. In addition, striking enhancement in the short channel margin and $mathrm{V}_{mathrm{th}}$ stability over a-IGZO was achieved. With thin gate-oxide (50 Å), the improved device performance was realized such as S.S. $times$ 0.41, DIBL $times$ 0.18, and $mathrm{I}_{mathrm{on}}$× 76.5 compared with a-IGZO TFT at $mathrm{T}_{mathrm{ox}}$ 100 Å.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"37 XI 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127800533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond BEOL互连创新:3nm及以上节点的材料、工艺和系统协同优化
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185299
G. Thareja, A. Pal, Xingye Wang, S. Dag, S. You, Shashank Sharma, Qing Zhu, C. L. Cervantes, Shinjae Hwang, Matthew Spuller, B. Ng, Pradeep S. Kumar, N. Tam, M. Gage, S. Deshpande, Zhiyuan Wu, A. Jansen, Liton Dey, Feng Chen, Xianjin Xie, K. Kashefizadeh, V. Reddy, Andy Lo, Zhebo Chen, S. Huey, Jianshe Tang, He Ren, M. Naik, Brian Brown, S. Kesapragada, Buvna Ayyagari-Sangamalli, E. Bazizi, Xianmin Tang
{"title":"BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond","authors":"G. Thareja, A. Pal, Xingye Wang, S. Dag, S. You, Shashank Sharma, Qing Zhu, C. L. Cervantes, Shinjae Hwang, Matthew Spuller, B. Ng, Pradeep S. Kumar, N. Tam, M. Gage, S. Deshpande, Zhiyuan Wu, A. Jansen, Liton Dey, Feng Chen, Xianjin Xie, K. Kashefizadeh, V. Reddy, Andy Lo, Zhebo Chen, S. Huey, Jianshe Tang, He Ren, M. Naik, Brian Brown, S. Kesapragada, Buvna Ayyagari-Sangamalli, E. Bazizi, Xianmin Tang","doi":"10.23919/VLSITechnologyandCir57934.2023.10185299","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185299","url":null,"abstract":"We present novel back-end-of-line (BEOL) copper interconnect integration for advanced technology nodes using integrated selective barrier copper barrier seed (CuBS) process, annealing and chemical mechanical planarization (CMP). Electrical tests (resistance, reliability) combined with Materials-to-Systems Co-Optimization (MSCO™) simulations confirm significant power-performance-area (PPA) gains for 3nm technology node and beyond.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128815450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering 基于Cell Stack工程的QLC可编程3D铁电NAND闪存
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185294
Sunghyun Yoon, Sung I. Hong, Daehyun Kim, Garam Choi, Young Mo Kim, Kyunghoon Min, Seiyon Kim, Myung-Hee Na, Seonyong Cha
{"title":"QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering","authors":"Sunghyun Yoon, Sung I. Hong, Daehyun Kim, Garam Choi, Young Mo Kim, Kyunghoon Min, Seiyon Kim, Myung-Hee Na, Seonyong Cha","doi":"10.23919/VLSITechnologyandCir57934.2023.10185294","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185294","url":null,"abstract":"3D ferroelectric NAND (Fe-NAND) Quad-level cell (QLC) operation has been demonstrated for the first time to our knowledge, using the 3D CTN NAND test vehicle for mass production. The 3D Fe-NAND is optimized by engineering the cell stack layers, enlarging a program/erase (PE) window up to 10.5 V. QLC operation is successfully verified with the minimum gap margin of 0.24 V. Endurance and data retention characteristics are also reported.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114510743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm 28nm无Bitcell修改的无ECC-Less多级SRAM物理不可克隆功能和127% PUF-to-Memory容量比
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185261
Joydeep Basu, Sachin Taneja, V. Rajanna, Tianqi Wang, M. Alioto
{"title":"ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm","authors":"Joydeep Basu, Sachin Taneja, V. Rajanna, Tianqi Wang, M. Alioto","doi":"10.23919/VLSITechnologyandCir57934.2023.10185261","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185261","url":null,"abstract":"A multi-level (2 bits/bitcell) SRAM PUF is introduced to uniquely enable ECC-less operation with PUF capacity exceeding storage capacity at no cell modification. The first PUF bit is generated from steady-state post-reset bitcell value with > 4X higher stability than conventional power-up. The second is simultaneously extracted from the transient response. Above-storage capacity and improved stability eliminate ECC down to the SRAM $V_{min}(0.6V)$ at 75-fJ/bit energy and 3.3% area overhead in 28 nm.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124883778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra-high Tunneling Electroresistance Ratio (2 × 104) & Endurance (108) in Oxide Semiconductor-Hafnia Self-rectifying (1.5 × 103) Ferroelectric Tunnel Junction 氧化物半导体-铪自整流(1.5 × 103)铁电隧道结的超高隧穿电阻比(2 × 104)和耐久性(108)
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185231
J. Hwang, Chaeheon Kim, Hunbeom Shin, Hwayoung Kim, S. K. Park, Sanghun Jeon
{"title":"Ultra-high Tunneling Electroresistance Ratio (2 × 104) & Endurance (108) in Oxide Semiconductor-Hafnia Self-rectifying (1.5 × 103) Ferroelectric Tunnel Junction","authors":"J. Hwang, Chaeheon Kim, Hunbeom Shin, Hwayoung Kim, S. K. Park, Sanghun Jeon","doi":"10.23919/VLSITechnologyandCir57934.2023.10185231","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185231","url":null,"abstract":"In this study, we present a remarkable improvement in the performance of hafnia-based ferroelectric tunnel junctions (FTJs) using oxygen scavenging technology and extremely low-damage (ELD) deposition, leading to a significant increase in the tunneling electroresistance ratio $({mathrm {TER}}) (gt 2 times 10^{4})$, on-current density $(gt 10^{-2}mathrm{A} /cm^{2})$, and self-rectifying ratio $({mathrm {RR}}) (gt 1.5 times 10^{3})$. First-principles DFT simulations were also used to evaluate how the asymmetric oxygen vacancy (VO) distribution affected FTJs. As an array-level demonstration of the proposed approach, we experimentally built an FTJ-based XNOR synapse array and verified its operation for binary neural networks (BNN).","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124394687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SP-PIM: A 22.41TFLOPS/W, 8.81Epochs/Sec Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for On-Device Learning SP-PIM:一种22.41TFLOPS/W, 8.81 epoch /Sec的基于本地错误预测的内存超级流水线处理加速器
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185428
Jung-Hoon Kim, Jaehoon Heo, Won-Ok Han, Jaeuk Kim, Joo-Young Kim
{"title":"SP-PIM: A 22.41TFLOPS/W, 8.81Epochs/Sec Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for On-Device Learning","authors":"Jung-Hoon Kim, Jaehoon Heo, Won-Ok Han, Jaeuk Kim, Joo-Young Kim","doi":"10.23919/VLSITechnologyandCir57934.2023.10185428","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185428","url":null,"abstract":"This paper presents SP-PIM that demonstrates real-time on-device learning based on the holistic, multi-level pipelining scheme enabled by local error prediction. It introduces the local error prediction unit to make the training algorithm pipelineable, while reducing computation overhead and overall external memory access based on power-of-two arithmetic operations and random weights. Its double-buffered PIM macro is designed for performing both forward propagation and gradient calculation, while the dual-sparsity-aware circuits exploit sparsity in activation and error. Finally, the 5.76mm2 SP-PIM chip fabricated in 28nm process achieves 8.81Epochs/Sec model training on chip with the state-of-the-art 560.6GFLOPS/mm2 area efficiency and 22.4TFLOPS/W power efficiency.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123612093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells 具有低读取延迟(18ns)，高非线性(>5000)和超低漏电流(~pA)自选择单元的16层3D垂直RRAM
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185341
Yaxin Ding, Jianguo Yang, Yu Liu, Jianfeng Gao, Yuan Wang, Pengfei Jiang, Shuxian Lv, Yuting Chen, Boping Wang, Wei Wei, Tiancheng Gong, Kanhao Xue, Q. Luo, Xiangshui Miao, Ming Liu
{"title":"16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells","authors":"Yaxin Ding, Jianguo Yang, Yu Liu, Jianfeng Gao, Yuan Wang, Pengfei Jiang, Shuxian Lv, Yuting Chen, Boping Wang, Wei Wei, Tiancheng Gong, Kanhao Xue, Q. Luo, Xiangshui Miao, Ming Liu","doi":"10.23919/VLSITechnologyandCir57934.2023.10185341","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185341","url":null,"abstract":"On-current and nonlinearity of selector-less RRAM are essential for improving the sensing speed and suppressing sneak path leakage respectively in 3D vertical crossbar structure. In this work, by using an oxide in which oxygen vacancies do not readily accumulate (NbOx) to prepare the memory layer, 50x on-state current density improvement is achieved with high nonlinearity of 5000. The maximum nonlinearity of this device is even higher $(8 times 10 ^{4}$ read @ 1.04 V). Furthermore, for the first time, we present a 16-layer 3D vertical RRAM. Other outstanding performances such as low off-current (~ pA), self-compliance and high endurance (> 108) are also demonstrated.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121654474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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