A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC

Abstract

This paper presents a low-voltage area-efficient through-silicon via (TSV) I/O for the high-bandwidth memory utilizing overlapped multiplexing driver, ISI compensators (hybrid equalizer, direct feedback 1-tap DFE) and quadrature error corrector. The proposed TSV I/O is implemented in 65nm CMOS process with emulated 12-stacked TSV. Measurement results show energy efficiency of 0.145pJ/b/pF and 30% timing margin with BER $\lt 10 ^{-12}$ at 15Gb/s with PRBS-31.