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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs 利用互补场效应管实现单位元可重构内存计算的写增强单端11T SRAM
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185283
W. You, Cheng-Yin Wang, Yih Wang, T. Chang, S. Liao
{"title":"Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs","authors":"W. You, Cheng-Yin Wang, Yih Wang, T. Chang, S. Liao","doi":"10.23919/VLSITechnologyandCir57934.2023.10185283","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185283","url":null,"abstract":"A write-enhanced single-ended 11T complementary FET (CFET) SRAM capable of performing reconfigurable compute-in-memory (CIM) using a single bitcell is presented for the first time. By leveraging the dummy PFETs within the standard 6T (or 8T) CFET SRAM layout, the write ability of the proposed 11T SRAM can be enhanced more than 2.5 times compared with the 6T (or 8T) SRAM without sacrificing the write half-selected disturb. In addition, the dummy PFETs acting as additional write transistors offers an opportunity to perform Boolean CIM with three reconfigurable schemes introduced in this work. By employing the CFET technology, the 11T CFET SRAM cell shows tiny area overhead compared with the 6T high current SRAM cell (HCC) using non-stacked CMOS and has a comparable footprint as the standard 8T CFET SRAM cell.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115116145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS/Microfluidics Point-of-Care SoC employing Square-Wave Voltcoulometry for Biosensing with Aptamers and CRISPR-Cas12a Enzymes 一种采用方波伏特库伦法的CMOS/微流控芯片，用于适体体和CRISPR-Cas12a酶的生物传感
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185383
Yan-Ting Hsiao, Shu-Yan Chuang, Hun Hou, Yun-Chun Su, Hsiu-Cheng Yeh, Hsin-Tzu Song, Yung-Jui Chang, Wei-Yang Weng, Y. Tsai, Pin-Yu Lin, Sih-Ying Chen, Yen-Ju Lin, Mei-Wei Lin, Jun-Chau Chien
{"title":"A CMOS/Microfluidics Point-of-Care SoC employing Square-Wave Voltcoulometry for Biosensing with Aptamers and CRISPR-Cas12a Enzymes","authors":"Yan-Ting Hsiao, Shu-Yan Chuang, Hun Hou, Yun-Chun Su, Hsiu-Cheng Yeh, Hsin-Tzu Song, Yung-Jui Chang, Wei-Yang Weng, Y. Tsai, Pin-Yu Lin, Sih-Ying Chen, Yen-Ju Lin, Mei-Wei Lin, Jun-Chau Chien","doi":"10.23919/VLSITechnologyandCir57934.2023.10185383","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185383","url":null,"abstract":"This paper presents a CMOS/microfluidics pointof-care (PoC)SoC for molecular detection using DNA aptamers and CRISPR-associated enzymes (Cas). We take advantage of the signaling property from the electron transfers of the redox reporters and present a square-wave voltcoulometry (SWVC) electrochemical readout circuit to achieve $gt 100times$ signal enhancement. The SoC is implemented in 180-nm CMOS technology, integrated with pH and temperature sensors, and consumes a total power of 2.4mW.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121249139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy 无碰撞构建立方体(BBCube) 3D:使用WoW和CoW的异构3D集成，以最低的比特访问能量提供TB/s带宽
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185277
Norio Chujo, K. Sakui, S. Sugatani, H. Ryoson, Tomoji Nakamura, T. Ohba
{"title":"Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy","authors":"Norio Chujo, K. Sakui, S. Sugatani, H. Ryoson, Tomoji Nakamura, T. Ohba","doi":"10.23919/VLSITechnologyandCir57934.2023.10185277","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185277","url":null,"abstract":"We propose a technology called BBCube 3D for AI and HPC applications, which need high bandwidth and power efficiency. BBCube 3D is constructed by heterogeneous 3D integration in which xPU (CPU, GPU etc.) chiplets and DRAM wafers are stacked using a combination of bumpless Wafer-on-Wafer and Chip-on-Wafer. BBCube 3D has the potential to achieve a bandwidth 30 times higher than DDR5 and four times higher than HBM2E with an bit access energy 1/20th that of DDR5 and 1/5th that of HBM2E.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124902309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F2 High-Density Integration 用于4F2高密度集成的具有BEOL 3D单片集成IGZO晶体管的非破坏性读取1T1C铁电电容存储电池
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185243
Zuopu Zhou, Leming Jiao, Qiwen Kong, Zijie Zheng, Kaizhen Han, Yue Chen, Chen Sun, Bich-Yen Nguyen, Xiao-Qing Gong
{"title":"Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F2 High-Density Integration","authors":"Zuopu Zhou, Leming Jiao, Qiwen Kong, Zijie Zheng, Kaizhen Han, Yue Chen, Chen Sun, Bich-Yen Nguyen, Xiao-Qing Gong","doi":"10.23919/VLSITechnologyandCir57934.2023.10185243","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185243","url":null,"abstract":"For the first time, we experimentally demonstrate a 1T1C ferroelectric capacitive memory (FCM) cell by vertically stacking the high-performance inversion-type FCM with the back-end-of-line (BEOL) IGZO channel access transistor having SS of 70 mV/decade. Based on the 1T1C configuration, we design and demonstrate a reading scheme by charge sharing between FCM and bit line capacitor. Thanks to the low write current of FCM, IGZO FET can provide sufficient current for the effective write operation even in highly scaled cells. With the 3D monolithic integration capability of IGZO FETs, we further propose a 1T1C FCM array structure to realize the highest density with $4mathrm{F}^{2}1 mathrm{T}1mathrm{C}$ cell size by stacking two layers of IGZO access transistors on top of the memory. We also validate the operation of the highly scaled $4mathrm{F}^{2}1 mathrm{T}1mathrm{C}$ cell with experiment-calibrated TCAD and SPICE simulation and predict that the 1T1C configuration is able to improve the delay and energy consumption by 87 times and 92 times respectively in the large-scale array compared with the FCM crossbar.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125854158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput 1Tb 3b/Cell 3d闪存，比特密度超过17Gb/mm2，接口3.2Gbps，程序吞吐量205MB/s
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185237
Mario Sako, T. Nakajima, Fumihiro Kono, T. Nakano, M. Fujiu, Junji Musha, Dai Nakamura, Naoaki Kanagawa, Y. Shimizu, K. Yanagidaira, T. Utsumi, T. Kawano, Yoshikazu Hosomura, Hiroki Yabe, M. Kano, H. Sugawara, A. H. Sravan, K. Hayashi, Toshiyuki Kouchi, Y. Watanabe
{"title":"A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput","authors":"Mario Sako, T. Nakajima, Fumihiro Kono, T. Nakano, M. Fujiu, Junji Musha, Dai Nakamura, Naoaki Kanagawa, Y. Shimizu, K. Yanagidaira, T. Utsumi, T. Kawano, Yoshikazu Hosomura, Hiroki Yabe, M. Kano, H. Sugawara, A. H. Sravan, K. Hayashi, Toshiyuki Kouchi, Y. Watanabe","doi":"10.23919/VLSITechnologyandCir57934.2023.10185237","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185237","url":null,"abstract":"A 210 + WL layers 1Tb 3b/cell 3D-Flash Memory achieves the high bit density of $gt17$ Gb/mm2. Physical 8plane architecture realizes low read latency of 40us and high program throughput of 205MB. High interface speed of 3.2Gbps is accomplished by reducing DQ area in the X direction to 41%. Hybrid row address decoders (X-DEC) can deal with the wiring congestion issue caused by the new architecture, minimizing the read latency degradation. One-pulse-two-strobe technique reduces sensing time by 18% and contributes to the achievement of 205MB/s program throughput.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125964022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package 3.0 Gb/s/pin的第四代F-chip与Toggle 5.0规格的16Tb NAND闪存多芯片封装
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185391
Youngmin Jo, Anil Kavala, Tongsung Kim, Byungkwan Chun, Jungjune Park, Tae-Sung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, C. Lee, Young-Dong Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Daehoon Na, Changyeon Yu, Jonghoon Park, Jaehwan Kim, Hyojin Kwon, Chan-ho Kim, M. Jung, Chanjin Park, Don-Iru Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, Sunghoi Hur
{"title":"A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package","authors":"Youngmin Jo, Anil Kavala, Tongsung Kim, Byungkwan Chun, Jungjune Park, Tae-Sung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, C. Lee, Young-Dong Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Daehoon Na, Changyeon Yu, Jonghoon Park, Jaehwan Kim, Hyojin Kwon, Chan-ho Kim, M. Jung, Chanjin Park, Don-Iru Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, Sunghoi Hur","doi":"10.23919/VLSITechnologyandCir57934.2023.10185391","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185391","url":null,"abstract":"A 1.2 V, 3.0 Gb/s/pin 16Tb NAND flash memory package with proposed 4th generation F-chip is presented. It is implemented with self-training techniques such as hybrid delay locked loop (DLL) and 3-step duty cycle correction (DCC) to overcome the speed bottlenecks in F-chip to NAND interface. Also, its multi-termination feature improves power efficiency by providing the use of different terminations on its interfaces. This work achieves an I/O speed of 3.0 Gb/s and power consumption of 58mW which are an improvement of 66% and 23.3%, respectively, in comparison with 3rd generation F-chip.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123587901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking 3nm 27.6 mbit /mm2自定时SRAM，支持0.48 - 1.2 V宽工作范围，远端预充电和弱位跟踪
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185429
Yumito Aoyagi, M. Yabuuchi, Tomotaka Tanaka, Y. Ishii, Yoshiaki Osada, Takaaki Nakazato, K. Nii, I-Hsin Wang, Y. Hsu, Hong-Chen Cheng, H. Liao, T. Chang
{"title":"A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking","authors":"Yumito Aoyagi, M. Yabuuchi, Tomotaka Tanaka, Y. Ishii, Yoshiaki Osada, Takaaki Nakazato, K. Nii, I-Hsin Wang, Y. Hsu, Hong-Chen Cheng, H. Liao, T. Chang","doi":"10.23919/VLSITechnologyandCir57934.2023.10185429","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185429","url":null,"abstract":"A 3-nm single-port (SP) 6T SRAM macro has been proposed using far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuit can reduce write cycle time to boost the pre-charge time and read cycle time to improve the trackability of supply voltage. We designed and fabricated a 434kbit SP SRAM macro on 3-nm FinFET technology. The bit density is $27.6-mathrm{Mbit} / mathrm{mm}^{2}$ and achieved 1.9GHz operation at $0.75 mathrm{~V}$ which is 35% faster than conventional performance.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116437034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET 基于50Gb/s dac的22nm FinFET多载波极性发射机
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185267
Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, S. Hoyos, S. Palermo
{"title":"A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET","authors":"Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, S. Hoyos, S. Palermo","doi":"10.23919/VLSITechnologyandCir57934.2023.10185267","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185267","url":null,"abstract":"A DAC-based polar transmitter (TX) for wireline applications efficiently implements jitter-robust multicarrier signaling with arbitrary modulation formats. 50Gb/s total data rate is supported by three parallel 5GS/s output drivers operating with baseband PAM-4 and mid-band (MB) and highband (HB) 16-state complex modulation on 5 and 10GHz orthogonal carriers. DAC amplitude resolution is 7b plus 2b predistortion for all drivers, while the polar MB and HB drivers also have 7b phase resolution. The TX DSP implements 8-tap FIR filtering on all bands. Fabricated in 22nm FinFET, the TX has 1.2$mathrm{V}_{mathrm{p}mathrm{p}mathrm{d}}$ swing and achieves 50Gb/sBER<$10^{-4}$ with both QAM-16 and APSK-4+12 modulations at 1. 68pJ/b.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129689496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer 利用基于fia的积分器和噪声整形SAR组合数字噪声耦合量化器简化抗混叠滤波器2MHz-BW 83dB-DR的24 osr
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185310
M. Fukazawa, T. Matsui
{"title":"A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer","authors":"M. Fukazawa, T. Matsui","doi":"10.23919/VLSITechnologyandCir57934.2023.10185310","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185310","url":null,"abstract":"This paper proposes a dynamic circuits-based discrete-time (DT) delta-sigma modulator (DSM) with 2MHz bandwidth (BW) at an oversampling ratio (OSR) of 24 to simplify anti-alias filter (AAF), flexible operating frequency, and power scalability. The proposed DSM consists of floating inverter amplifier (FIA) based integrators and an asynchronous SAR quantizer that combines passive noise shaping (PNS) and digital noise coupling (DNC) to enhance total noise shaping effect equal to the 3rd-order DSM. This DT-DSM achieves 83.1dB dynamic range (DR) while consuming 1.04mW, resulting in 175.9dB DR-based Schreier FoM.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128469908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exploring Power Savings of Gate-All-Around Cryogenic Technology 探索门-全方位低温技术的节能
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185420
V. Moroz, A. Svizhenko, Munkang Choi, P. Asenov, Jaehyun Lee
{"title":"Exploring Power Savings of Gate-All-Around Cryogenic Technology","authors":"V. Moroz, A. Svizhenko, Munkang Choi, P. Asenov, Jaehyun Lee","doi":"10.23919/VLSITechnologyandCir57934.2023.10185420","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185420","url":null,"abstract":"Operating CMOS circuits at cryogenic temperatures is becoming the most promising way to reduce power consumption of server farms [1–5]. This becomes possible by drastically reducing power supply voltage Vdd due to the steep subthreshold slope at low temperatures, avoiding 60 mV per decade “Boltzmann curse”. A key factor for reducing Vdd is a tight variability, which is enabled by the GAA (Gate-All-Around) technology [6–8]. In this work, we explore possible reduction of power consumption by operating GAA logic circuits at cryogenic temperatures. Besides, we estimate the combined power consumption of logic at cryogenic temperatures and the power required for cooling it.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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