3nm 27.6 mbit /mm2自定时SRAM，支持0.48 - 1.2 V宽工作范围，远端预充电和弱位跟踪

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185429

Yumito Aoyagi, M. Yabuuchi, Tomotaka Tanaka, Y. Ishii, Yoshiaki Osada, Takaaki Nakazato, K. Nii, I-Hsin Wang, Y. Hsu, Hong-Chen Cheng, H. Liao, T. Chang

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引用次数: 0

摘要

利用远端预充电(FPC)电路和弱比特(WB)跟踪电路，提出了一种3nm单口6T SRAM宏。该电路可以缩短写周期时间，提高预充电时间;缩短读周期时间，提高电源电压的可跟踪性。我们在3nm FinFET技术上设计并制造了一个434kbit SP SRAM宏。比特密度为$27.6-\ mathm {Mbit} / \ mathm {mm}^{2}$，在$0.75 \ mathm {~V}$下实现了1.9GHz的工作，比传统性能快35%。

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A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking

A 3-nm single-port (SP) 6T SRAM macro has been proposed using far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuit can reduce write cycle time to boost the pre-charge time and read cycle time to improve the trackability of supply voltage. We designed and fabricated a 434kbit SP SRAM macro on 3-nm FinFET technology. The bit density is $27.6-\mathrm{Mbit} / \mathrm{mm}^{2}$ and achieved 1.9GHz operation at $0.75 \mathrm{~V}$ which is 35% faster than conventional performance.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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