利用基于fia的积分器和噪声整形SAR组合数字噪声耦合量化器简化抗混叠滤波器2MHz-BW 83dB-DR的24 osr

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185310

M. Fukazawa, T. Matsui

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引用次数: 0

摘要

本文提出了一种基于动态电路的离散时间(DT) delta-sigma调制器(DSM)，其带宽为2MHz，过采样比(OSR)为24，以简化抗混叠滤波器(AAF)，灵活的工作频率和功率可扩展性。所提出的DSM由基于浮动逆变放大器(FIA)的积分器和异步SAR量化器组成，该量化器结合了被动噪声整形(PNS)和数字噪声耦合(DNC)，以提高与三阶DSM相同的总噪声整形效果。该DT-DSM在消耗1.04mW的情况下实现83.1dB动态范围(DR)，从而产生基于175.9dB DR的Schreier FoM。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer

This paper proposes a dynamic circuits-based discrete-time (DT) delta-sigma modulator (DSM) with 2MHz bandwidth (BW) at an oversampling ratio (OSR) of 24 to simplify anti-alias filter (AAF), flexible operating frequency, and power scalability. The proposed DSM consists of floating inverter amplifier (FIA) based integrators and an asynchronous SAR quantizer that combines passive noise shaping (PNS) and digital noise coupling (DNC) to enhance total noise shaping effect equal to the 3rd-order DSM. This DT-DSM achieves 83.1dB dynamic range (DR) while consuming 1.04mW, resulting in 175.9dB DR-based Schreier FoM.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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