Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs

Abstract

A write-enhanced single-ended 11T complementary FET (CFET) SRAM capable of performing reconfigurable compute-in-memory (CIM) using a single bitcell is presented for the first time. By leveraging the dummy PFETs within the standard 6T (or 8T) CFET SRAM layout, the write ability of the proposed 11T SRAM can be enhanced more than 2.5 times compared with the 6T (or 8T) SRAM without sacrificing the write half-selected disturb. In addition, the dummy PFETs acting as additional write transistors offers an opportunity to perform Boolean CIM with three reconfigurable schemes introduced in this work. By employing the CFET technology, the 11T CFET SRAM cell shows tiny area overhead compared with the 6T high current SRAM cell (HCC) using non-stacked CMOS and has a comparable footprint as the standard 8T CFET SRAM cell.