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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality 一种结合CPU和深度学习的通用内存计算处理器，提高CPU效率和增强数据局域性
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185311
Yuhao Ju, Yijie Wei, X. Chen, Jie Gu
{"title":"A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality","authors":"Yuhao Ju, Yijie Wei, X. Chen, Jie Gu","doi":"10.23919/VLSITechnologyandCir57934.2023.10185311","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185311","url":null,"abstract":"This work presents a general-purpose compute-in-memory (GPCIM) processor combining DNN operations and vector CPU. Utilizing special reconfigurability, dataflow, and instruction set, the 65nm test chip demonstrates a 28.5 TOPS/W DNN macro efficiency and a best-in-class peak CPU efficiency of 802GOPS/W. Due to a data locality flow, 37% to 55% end-to-end latency improvement on AI-related applications is achieved by eliminating inter-core data transfer.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130051569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory U-MRAM:无晶体管，高速(10ns)，低电压(0.6 V)，用于高密度数据存储器的无场单极MRAM
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185336
Ming-Hung Wu, Ming-Chun Hong, Ching-Kuei Shih, Yao-Jen Chang, Y. Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, S. Z. Rahaman, I. Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, S. Sheu, W. Lo, Shih-Chieh Chang, T. Hou
{"title":"U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory","authors":"Ming-Hung Wu, Ming-Chun Hong, Ching-Kuei Shih, Yao-Jen Chang, Y. Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, S. Z. Rahaman, I. Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, S. Sheu, W. Lo, Shih-Chieh Chang, T. Hou","doi":"10.23919/VLSITechnologyandCir57934.2023.10185336","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185336","url":null,"abstract":"U-MRAM, an enabler of a diode-selected cross-point MRAM array, is demonstrated using a mature device structure identical to STT-MRAM. U-MRAM exploits the probabilistic switching of thermal fluctuations using a single write voltage. The asymmetric synthetic antiferromagnetic layer (SAF) enables promising UMRAM properties, including low voltage (0.6 V), high speed (10 ns), excellent endurance (>$10^{10})$, and long retention (>10 years) without an external magnetic field. Diode-selected U-MRAM is a strong candidate for future high-density embedded memory.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132284371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A back-illuminated 6 μm SPAD depth sensor with PDE 36.5% at 940 nm via combination of dual diffraction structure and 2×2 on-chip lens 采用双衍射结构和2×2片上透镜，设计了一种背光6 μm SPAD深度传感器，PDE为36.5%，波长为940 nm
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185251
Y. Fujisaki, H. Tsugawa, K. Sakai, H. Kumagai, R. Nakamura, T. Ogita, S. Endo, T. Iwase, H. Takase, K. Yokochi, S. Yoshida, S. Shimada, Y. Otake, T. Wakano, H. Hiyama, K. Hagiwara, M. Arakawal, S. Matsumotol, H. Maeda, K. Sugihara, K. Takabayashi, M. Ono, K. Ishibashi, K. Yamamoto
{"title":"A back-illuminated 6 μm SPAD depth sensor with PDE 36.5% at 940 nm via combination of dual diffraction structure and 2×2 on-chip lens","authors":"Y. Fujisaki, H. Tsugawa, K. Sakai, H. Kumagai, R. Nakamura, T. Ogita, S. Endo, T. Iwase, H. Takase, K. Yokochi, S. Yoshida, S. Shimada, Y. Otake, T. Wakano, H. Hiyama, K. Hagiwara, M. Arakawal, S. Matsumotol, H. Maeda, K. Sugihara, K. Takabayashi, M. Ono, K. Ishibashi, K. Yamamoto","doi":"10.23919/VLSITechnologyandCir57934.2023.10185251","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185251","url":null,"abstract":"We present a back-illuminated 3D-stacked 6 $mu mathrm{m}$ single-photon avalanche diode (SPAD) sensor with very high photon detection efficiency (PDE) performance. To enhance PDE, a dual diffraction structure was combined with $2times 2$ on-chip lens (OCL) for the first time. A dual diffraction structure comprises a pyramid surface for diffraction (PSD) and periodic uneven structures by shallow trench for diffraction formed on the Si surface of light-facing and opposite sides, respectively. Additionally, PSD pitch and SiO2 film thickness buried in full trench isolation were optimized. Consequently, a PDE of 36.5% was achieved at $lambda=940$ nm, the world’s highest value. Owing to shield ring contact, crosstalk was reduced by about half compared to a conventionally plugged one.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132366204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance 具有无限循环寿命的嵌入式非易失性存储器
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185382
Sharadindu Gopal Kirtania, K. A. Aabrar, A. Khan, Shimeng Yu, S. Datta
{"title":"Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance","authors":"Sharadindu Gopal Kirtania, K. A. Aabrar, A. Khan, Shimeng Yu, S. Datta","doi":"10.23919/VLSITechnologyandCir57934.2023.10185382","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185382","url":null,"abstract":"We demonstrate a 1. 2x reduction in write voltage, 20x improvement in write speed and unlimited cycling endurance on a BEOL compatible Ferroelectric FET (FeFET) at 77K (Cold FeFET), justifying the potential of Cold-FEFET as a candidate for last-level cache memory in cryogenic high-performance computing (HPC) applications. Highly stable and tight threshold voltage distribution characteristics for both programmed and erased states in Cold-FeFET (pre and post cycling) is leveraged to reduce the read-current window specs and lower the write voltage amplitude and pulse compared to room temperature operation. In conjunction with logic CMOS operating at 77K, monolithic 3D integrated Cold-FeFET with unlimited write endurance provides an effective solution for future cryogenic HPC applications.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134537294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS 基于逆变器的5nm CMOS短距离模对模接口交流耦合收发器
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185334
Yoshinori Nishi, J. Poulton, Xi Chen, Sanquan Song, B. Zimmer, Walker J. Turner, S. Tell, N. Nedovic, John M. Wilson, W. Dally, C. T. Gray
{"title":"A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS","authors":"Yoshinori Nishi, J. Poulton, Xi Chen, Sanquan Song, B. Zimmer, Walker J. Turner, S. Tell, N. Nedovic, John M. Wilson, W. Dally, C. T. Gray","doi":"10.23919/VLSITechnologyandCir57934.2023.10185334","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185334","url":null,"abstract":"This paper presents an Inverter-based AC-coupled Toggle (ISR-ACT) transceiver targeted for short-reach die-to-die communication over silicon interposer or similar high-density interconnect. The ISR-ACT’s transmitter sends NRZ data through a small on-chip capacitor into the line. The receiver amplifies the low-swing pulses using a 1st-stage TIA to fully toggle the 2nd-stage output, where positive feedback to the input pad maintains the DC level on the line. Fabricated in a 5nm standard CMOS process, ISR-ACT link shows 0.66UI margin at 25.2Gb/s/wire on a 0.75V supply over a 1.2mm on-chip channel and demonstrates the potential to achieve 0.190pJ/bit.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS 在Si CMOS上单片堆叠一个平面FET和两个垂直FET非均质氧化半导体层的1mb1t1c 3D DRAM
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185263
Y. Okamoto, Y. Komura, T. Mizuguchi, T. Saito, M. Ito, K. Kimura, T. Onuki, Y. Ando, H. Sawai, T. Murakawa, H. Kunitake, T. Matsuzaki, H. Kimura, M. Fujita, M. Ikeda, S. Yamazaki
{"title":"1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS","authors":"Y. Okamoto, Y. Komura, T. Mizuguchi, T. Saito, M. Ito, K. Kimura, T. Onuki, Y. Ando, H. Sawai, T. Murakawa, H. Kunitake, T. Matsuzaki, H. Kimura, M. Fujita, M. Ikeda, S. Yamazaki","doi":"10.23919/VLSITechnologyandCir57934.2023.10185263","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185263","url":null,"abstract":"We have formed heterogeneous oxide semiconductor FETs (OSFETs) in one planar FET layer and two vertical FET (VFET) layers over Si by monolithically stacking OSFETs on top of Si CMOS. Formation of IOSIC DRAM memory cells in the VFET layers and a primary sense amplifier (1st SA) in the planar FET layer has realized a memory with different functions such as memory switching and signal amplification in different layers for the first time. As a result, special features, which are three-dimensional monolithic stacking of memory and long date retention, are implemented.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126984461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions 新型低热预算CMOS RMG:相对于传统高热预算栅极堆栈解决方案的性能和可靠性基准
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185317
J. Franco, H. Arimura, J. D. Marneffe, S. Brus, R. Ritzenthaler, E. Litta, K. Croes, B. Kaczer, N. Horiguchi
{"title":"Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions","authors":"J. Franco, H. Arimura, J. D. Marneffe, S. Brus, R. Ritzenthaler, E. Litta, K. Croes, B. Kaczer, N. Horiguchi","doi":"10.23919/VLSITechnologyandCir57934.2023.10185317","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185317","url":null,"abstract":"Low thermal budget gate stack fabrication is a key enabler for several upcoming CMOS technology innovations. For transistor stacking in Sequential 3D integrations, top device tiers need to be fabricated at reduced thermal budget [1] to preserve the functionality of the bottom tiers already in place. For monolithic CFET [2] fabrication, in a “RMGlast” flow the high temperature T reliability anneal $(sim 850^{circ}mathrm{C},sim 1.5mathrm{~s}$. spike) customarily used in conventional HKMG stacks to cure dielectric defects [3] can degrade the contact performance; conversely, moving the RMG module to earlier in the flow (\"RMG-first”) would impose thermal stability requirements for the HKMG stacks to endure the epi and contact module thermal budget (max $mathrm{T}sim 525^{circ}mathrm{C}$ for several hours), which would be particularly challenging for the tight effective Work Function (eWF) control [4] required by multi- $V_{text{th}}$ technologies. The development of novel low thermal budget gate stack solutions (Fig. 1) with competitive performance and reliability as compared to state-of-the-art RMG discussed here addresses these concerns.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116247627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
How Harsh is Space?–Equations That Connect Space and Ground VLSI 太空有多严酷?-连接空间和地面VLSI的方程
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185386
D. Kobayashi, K. Hirose
{"title":"How Harsh is Space?–Equations That Connect Space and Ground VLSI","authors":"D. Kobayashi, K. Hirose","doi":"10.23919/VLSITechnologyandCir57934.2023.10185386","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185386","url":null,"abstract":"Both space and ground are radiation-rich environments. Ensuring soft-error reliability is essential for both space and ground VLSI. Recent ground VLSI, particularly for automotive applications, has high reliability. It can be naturally considered for applications in space systems. However, estimating the space reliability of the ground VLSI is challenging. Space radiation is often regarded as ‘‘harsh’’ in comparison with ground radiation, but the magnitude of its harshness is unclear. The types of the radiation are different. Converting a ground soft-error reliability to space one is so far difficult. This study provides simple equations that can handle ground and space soft errors uniformly. The equations estimate the harshness of space at approximately 2500-times that of the ground. They also provide implications for the effects of dynamic voltage and frequency scaling on soft-error reliability. Advanced SOI and FinFET SRAMs respond to voltage scaling differently from classical bulk ones.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116648179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.75V 0.016mm2 12ENOB 7nm CMOS cyclic ADC with 1.5bit passive amplification stage and dynamic capacitance scaling 一个0.75V 0.016mm2 12ENOB 7nm CMOS循环ADC，具有1.5位无源放大级和动态电容缩放
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185426
T. Oshima, Keisuke Yamamoto, G. Ono
{"title":"A 0.75V 0.016mm2 12ENOB 7nm CMOS cyclic ADC with 1.5bit passive amplification stage and dynamic capacitance scaling","authors":"T. Oshima, Keisuke Yamamoto, G. Ono","doi":"10.23919/VLSITechnologyandCir57934.2023.10185426","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185426","url":null,"abstract":"A tiny but high-resolution cyclic ADC is presented with 7nm CMOS process. The 1.5bit/stage cyclic ADC performs fully differential sampling and passive residue amplification for small size and power. Proposed dynamic capacitance scaling overcomes limited power efficiency and input bandwidth of traditional cyclic ADCs. A time-assisted comparator makes ternary decision with minimal overhead. Measurement results of the 7nm CMOS prototype proved 4MS/s conversion rate and 74.0dB SNDR with 0.016mm2 and 0.86mW under 0.75V supply. This ADC advances the state of the art in design of high-resolution FinFET ADCs and cyclic ADCs.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123884163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and −248.6-dB FoMjitter 一种24- 30ghz级联QPLL，实现56.8 fs的RMS抖动和−248.6 db的FoMjitter
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185269
Li Wang, Zi-Ming Liu, C. Yue
{"title":"A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and −248.6-dB FoMjitter","authors":"Li Wang, Zi-Ming Liu, C. Yue","doi":"10.23919/VLSITechnologyandCir57934.2023.10185269","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185269","url":null,"abstract":"This paper presents a 24-30 GHz quadrature phase-locked loop (QPLL) by cascading a $1^{text{st}}$-stage low-jitter 7-GHz sub-sampling PLL (SSPLL) and a $2^{text{nd}}$-stage wideband 28-GHz dual-path (DP) SSPLL. A wide dynamic range ac-coupled SS-charge pump (AC-SSCP) is proposed in the $1^{text{st}}$-stage PLL to reduce the offset current in its output for lower jitter. The $2^{text{nd}}$ stage SSPLL boosts SS-phase detector (SSPD) gain using a dual-path topology to attain a 100-MHz wide loop bandwidth for suppressing the QVCO contribution to the overall output phase noise. Fabricated in 40-nm CMOS, the prototype achieves 56.8-fs integrated rms jitter, −55.6-dBc reference spur, −248.6-dB FoM $mathrm{jitter}^{mathrm{m}}$, and <7.0-fs jitter variation across the AC-SSCP output range (0.16-0.92 V) under a 1.1-V supply.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122158825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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