A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and −248.6-dB FoMjitter

Abstract

This paper presents a 24-30 GHz quadrature phase-locked loop (QPLL) by cascading a $1^{\text{st}}$-stage low-jitter 7-GHz sub-sampling PLL (SSPLL) and a $2^{\text{nd}}$-stage wideband 28-GHz dual-path (DP) SSPLL. A wide dynamic range ac-coupled SS-charge pump (AC-SSCP) is proposed in the $1^{\text{st}}$-stage PLL to reduce the offset current in its output for lower jitter. The $2^{\text{nd}}$ stage SSPLL boosts SS-phase detector (SSPD) gain using a dual-path topology to attain a 100-MHz wide loop bandwidth for suppressing the QVCO contribution to the overall output phase noise. Fabricated in 40-nm CMOS, the prototype achieves 56.8-fs integrated rms jitter, −55.6-dBc reference spur, −248.6-dB FoM $\mathrm{jitter}^{\mathrm{m}}$, and <7.0-fs jitter variation across the AC-SSCP output range (0.16-0.92 V) under a 1.1-V supply.