Sharadindu Gopal Kirtania, K. A. Aabrar, A. Khan, Shimeng Yu, S. Datta
{"title":"具有无限循环寿命的嵌入式非易失性存储器","authors":"Sharadindu Gopal Kirtania, K. A. Aabrar, A. Khan, Shimeng Yu, S. Datta","doi":"10.23919/VLSITechnologyandCir57934.2023.10185382","DOIUrl":null,"url":null,"abstract":"We demonstrate a 1. 2x reduction in write voltage, 20x improvement in write speed and unlimited cycling endurance on a BEOL compatible Ferroelectric FET (FeFET) at 77K (Cold FeFET), justifying the potential of Cold-FEFET as a candidate for last-level cache memory in cryogenic high-performance computing (HPC) applications. Highly stable and tight threshold voltage distribution characteristics for both programmed and erased states in Cold-FeFET (pre and post cycling) is leveraged to reduce the read-current window specs and lower the write voltage amplitude and pulse compared to room temperature operation. In conjunction with logic CMOS operating at 77K, monolithic 3D integrated Cold-FeFET with unlimited write endurance provides an effective solution for future cryogenic HPC applications.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance\",\"authors\":\"Sharadindu Gopal Kirtania, K. A. Aabrar, A. Khan, Shimeng Yu, S. Datta\",\"doi\":\"10.23919/VLSITechnologyandCir57934.2023.10185382\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate a 1. 2x reduction in write voltage, 20x improvement in write speed and unlimited cycling endurance on a BEOL compatible Ferroelectric FET (FeFET) at 77K (Cold FeFET), justifying the potential of Cold-FEFET as a candidate for last-level cache memory in cryogenic high-performance computing (HPC) applications. Highly stable and tight threshold voltage distribution characteristics for both programmed and erased states in Cold-FeFET (pre and post cycling) is leveraged to reduce the read-current window specs and lower the write voltage amplitude and pulse compared to room temperature operation. In conjunction with logic CMOS operating at 77K, monolithic 3D integrated Cold-FeFET with unlimited write endurance provides an effective solution for future cryogenic HPC applications.\",\"PeriodicalId\":317958,\"journal\":{\"name\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":\"333 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185382\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185382","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance
We demonstrate a 1. 2x reduction in write voltage, 20x improvement in write speed and unlimited cycling endurance on a BEOL compatible Ferroelectric FET (FeFET) at 77K (Cold FeFET), justifying the potential of Cold-FEFET as a candidate for last-level cache memory in cryogenic high-performance computing (HPC) applications. Highly stable and tight threshold voltage distribution characteristics for both programmed and erased states in Cold-FeFET (pre and post cycling) is leveraged to reduce the read-current window specs and lower the write voltage amplitude and pulse compared to room temperature operation. In conjunction with logic CMOS operating at 77K, monolithic 3D integrated Cold-FeFET with unlimited write endurance provides an effective solution for future cryogenic HPC applications.