Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions

Abstract

Low thermal budget gate stack fabrication is a key enabler for several upcoming CMOS technology innovations. For transistor stacking in Sequential 3D integrations, top device tiers need to be fabricated at reduced thermal budget [1] to preserve the functionality of the bottom tiers already in place. For monolithic CFET [2] fabrication, in a “RMGlast” flow the high temperature T reliability anneal $(\sim 850^{\circ}\mathrm{C},\sim 1.5\mathrm{~s}$. spike) customarily used in conventional HKMG stacks to cure dielectric defects [3] can degrade the contact performance; conversely, moving the RMG module to earlier in the flow ("RMG-first”) would impose thermal stability requirements for the HKMG stacks to endure the epi and contact module thermal budget (max $\mathrm{T}\sim 525^{\circ}\mathrm{C}$ for several hours), which would be particularly challenging for the tight effective Work Function (eWF) control [4] required by multi- $V_{\text{th}}$ technologies. The development of novel low thermal budget gate stack solutions (Fig. 1) with competitive performance and reliability as compared to state-of-the-art RMG discussed here addresses these concerns.