A 0.75V 0.016mm2 12ENOB 7nm CMOS cyclic ADC with 1.5bit passive amplification stage and dynamic capacitance scaling

Abstract

A tiny but high-resolution cyclic ADC is presented with 7nm CMOS process. The 1.5bit/stage cyclic ADC performs fully differential sampling and passive residue amplification for small size and power. Proposed dynamic capacitance scaling overcomes limited power efficiency and input bandwidth of traditional cyclic ADCs. A time-assisted comparator makes ternary decision with minimal overhead. Measurement results of the 7nm CMOS prototype proved 4MS/s conversion rate and 74.0dB SNDR with 0.016mm2 and 0.86mW under 0.75V supply. This ADC advances the state of the art in design of high-resolution FinFET ADCs and cyclic ADCs.