发布求助
文献互助 智能选刊 最新文献

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

筛选
英文 中文
A 93.5%-Efficiency 13.56-MHz-Bandwidth Optimal On/Off Tracking Active Rectifier with Fully Digital Feedback-Based Delay Control for Adaptive Efficiency Compensation 基于全数字反馈延迟控制的93.5%效率- 13.56 mhz带宽最优开/关跟踪有源整流器自适应效率补偿
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185395
Jisan Ahn, Hyun-Su Lee, Kyeongho Eom, Woojoong Jung, Hyung-Min Lee
{"title":"A 93.5%-Efficiency 13.56-MHz-Bandwidth Optimal On/Off Tracking Active Rectifier with Fully Digital Feedback-Based Delay Control for Adaptive Efficiency Compensation","authors":"Jisan Ahn, Hyun-Su Lee, Kyeongho Eom, Woojoong Jung, Hyung-Min Lee","doi":"10.23919/VLSITechnologyandCir57934.2023.10185395","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185395","url":null,"abstract":"This paper presents a high-efficiency adaptive active rectifier with fully digital feedback-based delay controllers (DFDC) to rapidly trace optimal on/off timing against input/load variations. Thanks to the real-time power-saving mode control, the proposed rectifier achieved high power conversion efficiency (PCE) of 93.5% and voltage conversion ratio (VCR) of 96.3%. The rectifier adaptively adjusts on/off timing with fast 13. 56MHz tracking loop bandwidth.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125060776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Epitaxial Strain Control of HfxZr1-xO2 with Sub-nm IGZO Seed Layer Achieving EOT=0.44 nm for DRAM Cell Capacitor 亚纳米IGZO种子层HfxZr1-xO2外延应变控制实现EOT=0.44 nm的DRAM电池电容器
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185400
Seongho Kim, Young-Keun Park, Gyusoup Lee, E. Shin, W. Ko, Hi Deok Lee, Ga-Won Lee, B. Cho
{"title":"Epitaxial Strain Control of HfxZr1-xO2 with Sub-nm IGZO Seed Layer Achieving EOT=0.44 nm for DRAM Cell Capacitor","authors":"Seongho Kim, Young-Keun Park, Gyusoup Lee, E. Shin, W. Ko, Hi Deok Lee, Ga-Won Lee, B. Cho","doi":"10.23919/VLSITechnologyandCir57934.2023.10185400","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185400","url":null,"abstract":"We propose for the first time a method to crystallize 4.5 nm H$mathrm{f}_{05} Z mathrm{r}_{05}mathrm{O}_{2}$ (HZO) in the ferroelectric orthorhombic phase (0-phase) by using a sub-nm InGaZnO (IGZO) seed layer. Atomic mismatch between IGZO and HZO layers introduces epitaxial strain, inducing ferroelectric phase crystallization even at thickness of 4.5 nm. HZO/IGZO achieved an EOT of 0.44 nm, coercive voltage of 0.51 V, and high endurance >1014. Hence, HZO/IGZO is a promising candidate for next generation high-k dielectric in DRAM capacitor applications.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123839596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge Pianissimo:一种亚毫瓦级深度神经网络加速器，具有渐进式逐位数据路径架构，用于边缘自适应推理
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185293
Jun Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
{"title":"Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge","authors":"Jun Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura","doi":"10.23919/VLSITechnologyandCir57934.2023.10185293","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185293","url":null,"abstract":"Pianissimo is a sub-mW class inference accelerator that adaptively responds to the changing edge environmental conditions with a progressive bit-by-bit datapath architecture. SWHW cooperative control with the custom RISC and the HW counters allows Pianissimo adaptive/mixed precision and block skip, providing a better accuracy-computation tradeoff for low-power edge AI. The 40 nm chip, with 1104 KB memory, dissipates 793-1032$mu$W at 0.7 V on MobileNetVl, achieving 0. 49-1.25TOPS/W at this ultra-low power range.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126315831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations 求解耦合偏微分方程的位串行计算加速器
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185162
Junjie Mu, Chengshuo Yu, T. T. Kim, Bongjin Kim
{"title":"A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations","authors":"Junjie Mu, Chengshuo Yu, T. T. Kim, Bongjin Kim","doi":"10.23919/VLSITechnologyandCir57934.2023.10185162","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185162","url":null,"abstract":"This work presents a bit-serial computing hardware accelerator with a $20 times 10$ fully-parallel processing element (PE) array for solving one-/two-dimensional (1D/2D) coupled partial differential equations (PDEs) with key highlights, including reconfigurability, scalable PE architecture with minimal energy/area overhead, and high parallelism. The test chip is fabricated with a 65nm technology, occupying a core area of 0.458mm2 and consuming 107.8pJ and 110.8pJ, respectively, for solving 1D and 2D coupled PDEs at 1V and 25.6MHz.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128356196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm 具有2.4 pJ/像素能量和40 nm深度神经网络活性降低两个数量级的视觉内容不可知新颖性检测引擎
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185225
Animesh Gupta, Sayan Kumar, V. Rajanna, Sachin Taneja, Massimo Alioto
{"title":"Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm","authors":"Animesh Gupta, Sayan Kumar, V. Rajanna, Sachin Taneja, Massimo Alioto","doi":"10.23919/VLSITechnologyandCir57934.2023.10185225","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185225","url":null,"abstract":"An engine to identify frames with novel content in a video stream is proposed as additional vision pipeline stage following conventional saliency detection. Based on connected component analysis with mean-center tracking, its complexity is reduced to linear compared to quadratic in prior art. This introduces frame-level temporal sparsity for subsequent DNN activity/power reduction (177X beyond saliency detection). 2.4 pJ/pixel energy is achieved in 40 nm.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115008218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load 具有低纹波双采样PD的参考采样锁相环，在12pf输入负载下实现- 80 dbc参考杂散和- 259 db FoM
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185259
Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka
{"title":"A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load","authors":"Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka","doi":"10.23919/VLSITechnologyandCir57934.2023.10185259","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185259","url":null,"abstract":"A reference-sampling PLL (RSPLL) with low-ripple double-sampling phase detector (DSPD) is proposed to lower the PD’s in-band phase noise (PN) by 3dB without raising PLL’s input load and crystal oscillator’s (XO’s) power consumption. A unity-gain buffer (UGB) based charger and a multiplexed dummy sampler are proposed to reduce PLL’s input load by a factor of 4 without compromising spur and jitter performances. With a 100-MHz input reference, the prototype in 65-nm CMOS achieves an RMS jitter of 63fs with a spur level of −80dBc. The total power consumption is 3.1mW at 3.4GHz.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128898875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 一个2GS/s 11b 8x交错ADC，具有9.2 ENOB和69.9dB SFDR, 28nm CMOS
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185370
Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, L. Bertulessi, S. Levantino, A. Lacaita, C. Samori, A. Bonfanti
{"title":"A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS","authors":"Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, L. Bertulessi, S. Levantino, A. Lacaita, C. Samori, A. Bonfanti","doi":"10.23919/VLSITechnologyandCir57934.2023.10185370","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185370","url":null,"abstract":"A 2GS/s 11b 8x-interleaved ADC is presented where flipped-voltage-follower-based reference buffers attenuate channel interactions and a set of on-chip background digital calibrations mitigate channel mismatches. A high-linearity input buffer is included which does not degrade ADC performances. Implemented in a 28nm CMOS technology, the ADC achieves 57.3dB SNDR and 69.9dB SFDR close to the Nyquist frequency. The interleaved ADC maintains (within 1.2 dB) the same SNDR level of the individual channel over the 1GHz input bandwidth.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134548003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Record High Active Boron Doping using Low Temperature In-situ CVD: Enabling Sub-5×10−10 Ω-cm2 ρc from Cryogenic (5 K) to Room Temperature 低温原位CVD记录高活性硼掺杂:使Sub-5×10−10 Ω-cm2 ρc从低温(5 K)到室温
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185320
Gerui Zheng, Yuxuan Wang, Haiwen Xu, R. Khazaka, Lutz Muehlenbein, Sheng Luo, Xuanqi Chen, Rui Shao, Zijie Zheng, G. Liang, Xiao-Qing Gong
{"title":"Record High Active Boron Doping using Low Temperature In-situ CVD: Enabling Sub-5×10−10 Ω-cm2 ρc from Cryogenic (5 K) to Room Temperature","authors":"Gerui Zheng, Yuxuan Wang, Haiwen Xu, R. Khazaka, Lutz Muehlenbein, Sheng Luo, Xuanqi Chen, Rui Shao, Zijie Zheng, G. Liang, Xiao-Qing Gong","doi":"10.23919/VLSITechnologyandCir57934.2023.10185320","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185320","url":null,"abstract":"We report the first demonstration of active boron (B) doping concentration $left(N_{A}right)$ higher than $2.50 times 10^{21} mathrm{~cm}^{-3}$ in high Ge content (> 65%) Si1-x Gex using In-situ growth technique with a low temperature below 500 °C. We achieve excellent uniformities of Si1-x Gex thickness and resistivity across the entire 300 mm wafer and obtain an ultra-low as-deposited specific contact resistivity $left(rho_{c}right)$ down to $2.9 pm 2.8 times 10^{-10} Omega-mathrm{cm}^{2}$ on the sample with a high average active doping concentration $left(N_{A}right)$ of $2.80 times 10^{21} mathrm{~cm}^{-3}$ and Ge composition of 65%. We further detail the progression of the selective growth of such $mathrm{Si}_{1 cdot x} mathrm{Ge}_{x}$ film on advanced 3D structures. Using metal $/ mathrm{Si}_{1-x} mathrm{Ge}_{x}$ ladder TLM (LTLM) structures, we investigate the contact properties from room temperature to cryogenic temperatures as low as $5 mathrm{~K}$, disclosing for the first time the insignificant change of $rho_{c}$ at such ultra-low $rho_{c}$ regimes.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131132945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
First Demonstration of Work Function-Engineered BEOL-Compatible IGZO Non-Volatile MFMIS AFeFETs and Their Co-Integration with Volatile-AFeFETs 工作函数设计的beol兼容IGZO非挥发性MFMIS效应及其与挥发性效应的协整
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185355
Zijie Zheng, Leming Jiao, Zuopu Zhou, Yuxuan Wang, Long Liu, Kaizhen Han, Chen Sun, Qiwen Kong, Dong Zhang, Xiaolin Wang, Kai Ni, Xiao-Qing Gong
{"title":"First Demonstration of Work Function-Engineered BEOL-Compatible IGZO Non-Volatile MFMIS AFeFETs and Their Co-Integration with Volatile-AFeFETs","authors":"Zijie Zheng, Leming Jiao, Zuopu Zhou, Yuxuan Wang, Long Liu, Kaizhen Han, Chen Sun, Qiwen Kong, Dong Zhang, Xiaolin Wang, Kai Ni, Xiao-Qing Gong","doi":"10.23919/VLSITechnologyandCir57934.2023.10185355","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185355","url":null,"abstract":"For the first time, non-volatile antiferroelectric FETs (NVAFeFETs) with a metal-AFe-metal-insulator-semiconductor (MFMIS) structure are realized employing a replaced floating gate (FG), showing ultrahigh endurance over $2 times 10 ^{9}$ cycles. A device with channel length LCH of 41 nm achieves a memory window of 1.8 V. These are made possible through a comprehensive understanding of work function (WF)-engineered NV-AFe capacitors having various metals of Al, Pd, and Pt, including the first study of their temperature-dependent characteristics. The promise of our NV-AFeFETs and WF engineering is further highlighted by co-integrating synapses (NVAFeFETs) and neurons (volatile-AFeFETs) using the same device architecture to enable hardware-implemented neuromorphic computing.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":" 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132075421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter 4.4 GS/s 220 MHz ΣΔ ADC，带线性化后门控制GmC滤波器
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI: 10.23919/VLSITechnologyandCir57934.2023.10185281
Julius Edler, Marcel Runge, Sebastian Linnhoff, F. Gerfers
{"title":"A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter","authors":"Julius Edler, Marcel Runge, Sebastian Linnhoff, F. Gerfers","doi":"10.23919/VLSITechnologyandCir57934.2023.10185281","DOIUrl":"https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185281","url":null,"abstract":"This paper presents a 4.4 GS/s220Mhz bandwidth continuous time sigma delta modulator with a linear GmC loop filter enabled by voltage tracking through multi-bit feedback and an active linearization scheme employing the back-gate node. An auxiliary amplifier drives the back-gate node of the main differential pair to linearize the overall $mathrm{G}_{mathrm{m}}(mathrm{V}_{mathrm{i}mathrm{n}}$) curve. The fabricated prototype shows a 27dB reduction in third order intermodulation (IM3) products down to -78dBc and a SNDR of 62dB while consuming 22 mW, reaching excellent 49fJ/step power efficiency.","PeriodicalId":317958,"journal":{"name":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133458760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信