A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load

Abstract

A reference-sampling PLL (RSPLL) with low-ripple double-sampling phase detector (DSPD) is proposed to lower the PD’s in-band phase noise (PN) by 3dB without raising PLL’s input load and crystal oscillator’s (XO’s) power consumption. A unity-gain buffer (UGB) based charger and a multiplexed dummy sampler are proposed to reduce PLL’s input load by a factor of 4 without compromising spur and jitter performances. With a 100-MHz input reference, the prototype in 65-nm CMOS achieves an RMS jitter of 63fs with a spur level of −80dBc. The total power consumption is 3.1mW at 3.4GHz.