求解耦合偏微分方程的位串行计算加速器

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185162

Junjie Mu, Chengshuo Yu, T. T. Kim, Bongjin Kim

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引用次数: 0

摘要

这项工作提出了一个位串行计算硬件加速器，其具有$20 \ × 10$的全并行处理元件(PE)阵列，用于求解一/二维(1D/2D)耦合偏微分方程(PDEs)，其关键亮点包括可重构性，可扩展的PE架构，具有最小的能量/面积开销和高并行性。测试芯片采用65nm工艺制作，核心面积为0.458mm2，功耗分别为107.8pJ和110.8pJ，用于求解1V和25.6MHz的1D和2D耦合pde。

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A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations

This work presents a bit-serial computing hardware accelerator with a $20 \times 10$ fully-parallel processing element (PE) array for solving one-/two-dimensional (1D/2D) coupled partial differential equations (PDEs) with key highlights, including reconfigurability, scalable PE architecture with minimal energy/area overhead, and high parallelism. The test chip is fabricated with a 65nm technology, occupying a core area of 0.458mm2 and consuming 107.8pJ and 110.8pJ, respectively, for solving 1D and 2D coupled PDEs at 1V and 25.6MHz.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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