Pianissimo:一种亚毫瓦级深度神经网络加速器，具有渐进式逐位数据路径架构，用于边缘自适应推理

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185293

Jun Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

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摘要

Pianissimo是一种亚毫瓦级的推理加速器，它通过渐进的逐位数据路径架构自适应地响应不断变化的边缘环境条件。SWHW与定制RISC和HW计数器的协同控制允许Pianissimo自适应/混合精度和块跳过，为低功耗边缘AI提供更好的精度计算权衡。40nm芯片，1104 KB内存，在0.7 V下消耗793-1032$\mu$W，在MobileNetVl上实现0。49-1.25TOPS/W在这个超低功率范围。

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Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge

Pianissimo is a sub-mW class inference accelerator that adaptively responds to the changing edge environmental conditions with a progressive bit-by-bit datapath architecture. SWHW cooperative control with the custom RISC and the HW counters allows Pianissimo adaptive/mixed precision and block skip, providing a better accuracy-computation tradeoff for low-power edge AI. The 40 nm chip, with 1104 KB memory, dissipates 793-1032$\mu$W at 0.7 V on MobileNetVl, achieving 0. 49-1.25TOPS/W at this ultra-low power range.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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