一个2GS/s 11b 8x交错ADC，具有9.2 ENOB和69.9dB SFDR, 28nm CMOS

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2023-06-11 DOI:10.23919/VLSITechnologyandCir57934.2023.10185370

Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, L. Bertulessi, S. Levantino, A. Lacaita, C. Samori, A. Bonfanti

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引用次数: 0

摘要

提出了一种2GS/s 11b 8x交错ADC，其中基于翻转电压跟随器的参考缓冲器衰减通道相互作用，一组片上背景数字校准减轻通道不匹配。高线性输入缓冲器不会降低ADC的性能。该ADC采用28nm CMOS技术实现，实现了接近奈奎斯特频率的57.3dB SNDR和69.9dB SFDR。交错ADC在1GHz输入带宽上保持单个通道相同的SNDR水平(在1.2 dB内)。

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A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS

A 2GS/s 11b 8x-interleaved ADC is presented where flipped-voltage-follower-based reference buffers attenuate channel interactions and a set of on-chip background digital calibrations mitigate channel mismatches. A high-linearity input buffer is included which does not degrade ADC performances. Implemented in a 28nm CMOS technology, the ADC achieves 57.3dB SNDR and 69.9dB SFDR close to the Nyquist frequency. The interleaved ADC maintains (within 1.2 dB) the same SNDR level of the individual channel over the 1GHz input bandwidth.

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2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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